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falc ? -lh e1/t1/j1 framer and line interface component for long and short haul applications peb 2255 version 1.3 data sheet, ds 1, july 2000 datacom never stop thinking.
edition 2000-07 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 7/13/00. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
datacom falc ? -lh e1/t1/j1 framer and line interface component for long and short haul applications peb 2255 version 1.3 data sheet, ds 1, july 2000 never stop thinking.
for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com peb 2255 revision history: 2000-07 ds 1 previous version: preliminary data sheet ds1 page subjects (major changes since last revision)
peb 2255 falc-lh v1.3 data sheet 5 2000-07 preface the falc ? -lh framer and line interface component is designed to fulfill all required interfacing between an analog e1/t1/j1 line and the digital pcm system highway/h.100 bus. the digital functions as well as the analog characteristics are configured via a flexible microprocessor interface.
peb 2255 falc-lh v1.3 data sheet 6 2000-07 organization of this document this data sheet is organized as follows: chapter 1 , introduction gives a general description of the product and its family, lists the key features, and presents some typical applications. chapter 2 , pin descriptions lists pin locations with associated signals, categorizes signals according to function, and describes signals. chapter 3 to chapter 5 , functional description e1/t1/j1 these chapters describe the functional blocks and principle operation modes, organized into separate sections for e1 and t1/j1 operation chapter 6 and chapter 7 , operational description e1/t1/j1 shows the operation modes and how they are to be initialized (separately for e1 and t1/j1). chapter 8 , signaling controller operating modes describes signaling controller functions for both e1 and t1/j1 operation. chapter 9 and chapter 10 , e1 registers and t1/j1 registers gives a detailed description of all implemented registers and how to use them in different applications/configurations. chapter 11 , electrical characteristics specifies maximum ratings, dc and ac characteristics. chapter 12 , package outlines shows the mechanical values of the device package. chapter 13 , appendix gives an example for overvoltage protection and information about application notes and other support. chapter 14 , glossary index
peb 2255 falc-lh v1.3 data sheet 7 2000-07 related documentation your comments we welcome your comments on this document. we are continuously trying improving our documentation. please send your remarks and suggestions by e-mail to sc.docu_comments@infineon.com please provide in the subject of your e-mail: device name (falc ? -lh), device number (peb 2255), device version (version 1.3), and in the body of your e-mail: document type (data sheet), issue date (2000-07) and document revision number (ds 1). this document refers to the following international standards (in alphabetical/numerical order): ansi/eia-656 ansi t1.102 ansi t1. 4 03 at & tp u b 4 3 8 02 at & tp u b5 4 016 at & tp u b62 4 11 esd ass. standard eos/esd-5.1-1 99 3 etsi ets 300 011 etis ets 300 166 etsi ets 300 233 etsi ets 300 32 4 etsi ets 300 3 4 7 etsi tbr12 etsi tbr13 fcc part6 8 gr-253-core gr- 499 -core gr-10 89 -core h.100 h-mvip ieee 11 49 .1 it u -t g.703 it u -t g.70 4 it u -t g.705 it u -t g.706 it u -t g.732 it u -t g.735 it u -t g.736 it u -t g.737 it u -t g.73 8 it u -t g.73 9 it u -t g. 8 23 it u -t g. 8 2 4 it u -t g. 9 62 it u -t g. 9 63 it u -t g. 9 6 4 it u -t i. 4 31 it u - q .703 jt-g703 jt-g70 4 jt-g706 jt-i 4 31 mil-std. 88 3d tr-ts y -00000 9 u l1 4 5 9
peb 2255 falc-lh v1.3 table of contents page data sheet 8 2000-07 1 introduction ............................................... 17 1.1 features................................................... 1 8 1.2 logicsymbol ............................................... 21 1.3 typicalapplications .......................................... 22 2 pin descriptions ........................................... 2 4 2.1 pindiagram ................................................ 2 4 2.2 pindefinitionsandfunctions .................................. 25 3 functional description e1/t1/j1 .............................. 4 5 3.1 functionaloverview ......................................... 4 5 3.2 blockdiagram .............................................. 4 6 3.3 functionalblocks............................................ 4 7 3.3.1 microprocessorinterface .................................... 4 7 3.3.1.1 mixedbyte/wordaccesstothefifos ....................... 4 7 3.3.1.2 fifostructure .......................................... 49 3.3.1.3 interruptinterface ....................................... 50 3.3.2 boundary scan interface . . . ................................. 52 4 functional description e1 ................................... 5 4 4 .1 receivepathine1mode ..................................... 5 4 4 .1.1 receiveequalizationnetwork(e1) ............................ 55 4 .1.2 receive line attenuation indication (e1) . . ...................... 55 4 .1.3 receiveclockanddatarecovery(e1) ........................ 55 4 .1. 4 receivelinecoding(e1) ................................... 55 4 .1.5 loss of signal detection (e1) ................................ 57 4 .1.6 receivejitterattenuator(e1) ................................ 5 8 4 .1.7 jittertolerance(e1) ....................................... 60 4 .1. 8 outputjitter(e1) .......................................... 60 4 .1. 9 transmit jitter attenuator (e1) ................................ 61 4 .1.10 framer/synchronizer ....................................... 62 4 .1.11 receiveelasticbuffer(e1) .................................. 63 4 .1.12 receivesignalingcontroller(e1) ............................. 66 4 .1.12.1 hdlcorlapdaccess ................................... 66 4 .1.12.2 sabitaccess(e1) ....................................... 66 4 .1.12.3 channel associated signaling cas (e1, serial mode) . .......... 66 4 .1.12. 4 channel associated signaling cas (e1, p access mode) . . ..... 6 8 4 .2 systeminterfaceine1mode................................... 6 9 4 .2.1 timeslotassigner(e1)..................................... 72 4 .3 transmitpathine1mode ..................................... 73 4 .3.1 transmitsignalingcontroller(e1)............................. 76 4 .3.1.1 hdlcorlapdaccess ................................... 76 4 .3.1.2 sabitaccess(e1) ....................................... 76 4 .3.1.3 channel associated signaling cas (e1, serial access mode) ..... 76
peb 2255 falc-lh v1.3 table of contents page data sheet 9 2000-07 4 .3.1. 4 channel associated signaling cas (e1, p access mode) . . ..... 77 4 .3.2 transmitelasticbuffer(e1).................................. 77 4 .3.3 transmitter(e1)........................................... 7 8 4 .3. 4 transmitlineinterface(e1) ................................. 7 9 4 .3.5 programmable pulse shaper (e1) . . ........................... 8 0 4 .3.6 transmitlinemonitor(e1) .................................. 8 0 4 . 4 framer operating modes (e1) . ................................. 8 2 4 . 4 .1 general ................................................. 8 2 4 . 4 .2 doubleframeformat(e1) ................................... 8 3 4 . 4 .2.1 transmittransparentmodes............................... 8 3 4 . 4 .2.2 synchronization procedure ................................ 84 4 . 4 .2.3 a-bitaccess ........................................... 8 5 4 . 4 .2. 4 sa-bitaccess ......................................... 8 5 4 . 4 .3 crc-multiframe (e1) . ...................................... 8 6 4 . 4 .3.1 synchronization procedure ................................ 8 7 4 . 4 .3.2 automaticforceresynchronization(e1) ..................... 88 4 . 4 .3.3 floatingmultiframealignmentwindow(e1) ................... 88 4 . 4 .3. 4 crc 4 performancemonitoring(e1) ......................... 88 4 . 4 .3.5 modified crc 4 multiframealignmentalgorithm(e1) ............ 88 4 . 4 .3.6 a-bitaccess(e1)........................................ 89 4 . 4 .3.7 sa-bitaccess(e1)...................................... 9 0 4 . 4 .3. 8 e-bitaccess(e1)........................................ 9 1 4 .5 additionalfunctions(e1)...................................... 9 3 4 .5.1 errorperformancemonitoringandalarmhandling ................ 9 3 4 .5.2 auto modes . . ............................................ 94 4 .5.3 error counter . ............................................ 9 5 4 .5. 4 erroredsecond ........................................... 9 5 4 .5.5 secondtimer ............................................ 9 5 4 .5.6 in-band loop generation and detection . . ...................... 9 5 4 .5.7 timeslot0transparentmode ............................... 9 6 4 .6 testfunctions(e1) .......................................... 9 7 4 .6.1 pseudo-random bit sequence generation and monitor . . .......... 9 7 4 .6.2 remote loop . ............................................ 9 7 4 .6.3 payload loop back . . ...................................... 98 4 .6. 4 localloop ............................................... 99 4 .6.5 single channel loop back . ................................ 100 4 .6.6 alarmsimulation(e1) ..................................... 101 5 functional description t1/j1 ................................ 102 5.1 receivepathint1/j1mode .................................. 102 5.1.1 receiveequalizationnetwork(t1/j1)......................... 103 5.1.2 receive line attenuation indication (t1/j1) .................... 103 5.1.3 receiveclockanddatarecovery(t1/j1) ..................... 103
peb 2255 falc-lh v1.3 table of contents page data sheet 10 2000-07 5.1. 4 receivelinecoding(t1/j1) ................................ 103 5.1.5 loss of signal detection (t1/j1) . . . .......................... 10 4 5.1.6 receivejitterattenuator(t1/j1) ............................. 105 5.1.7 jittertolerance(t1/j1) .................................... 10 8 5.1. 8 outputjitter(t1/j1)....................................... 10 9 5.1. 9 transmit jitter attenuator (t1/j1) . . .......................... 10 9 5.1.10 framer/synchronizer(t1/j1)................................ 110 5.1.11 receiveelasticbuffer(t1/j1) ............................... 111 5.1.12 receivesignalingcontroller(t1/j1) .......................... 115 5.1.12.1 hdlc/sdlcorlapdaccess ............................. 115 5.1.12.2 cas bit-robbing (t1/j1, serial access mode) . . ............... 115 5.1.12.3 cas bit-robbing (t1/j1, paccessmode) ................... 116 5.1.12. 4 bit oriented messages in esf-dl channel (t1/j1) . . . ......... 116 5.1.12.5 datalinkaccessinf72format(t1/j1) ..................... 116 5.2 systeminterfaceint1/j1mode ............................... 116 5.2.1 timeslotassigner(t1/j1) ................................. 121 5.3 transmitpathint1/j1mode.................................. 123 5.3.1 transmitsignalingcontroller(t1/j1) ......................... 12 9 5.3.1.1 hdlcorlapdaccess .................................. 12 9 5.3.1.2 cas bit-robbing (t1/j1) . . ................................ 12 9 5.3.1.3 data link access in esf/f2 4 andf72format(t1/j1) .......... 130 5.3.2 transmitelasticbuffer(t1/j1) .............................. 131 5.3.3 transmitter(t1/j1) ....................................... 133 5.3. 4 transmitlineinterface(t1/j1) .............................. 13 4 5.3.5 programmable pulse shaper and line build-out (t1/j1) . ......... 135 5.3.6 transmitlinemonitor(t1/j1) ............................... 136 5. 4 framer operating modes (t1/j1) .............................. 137 5. 4 .1 general ................................................ 137 5. 4 .2 generalaspectsofsynchronization .......................... 137 5. 4 .3 4 -frame multiframe (f 4 format,t1/j1) ....................... 1 4 0 5. 4 .3.1 synchronization procedure ............................... 1 4 0 5. 4 . 4 12-frame multiframe (d 4 orsfformat,t1/j1) ................. 1 4 0 5. 4 . 4 .1 synchronization procedure ............................... 1 4 1 5. 4 .5 extended superframe (f2 4 oresfformat,t1/j1)............... 1 4 2 5. 4 .5.1 synchronization procedures .............................. 1 4 2 5. 4 .5.2 remotealarm(yellowalarm)generation/detection ............ 1 44 5. 4 .5.3 crc6 generation and checking (t1/j1) ..................... 1 44 5. 4 .6 72-frame multiframe (slc 9 6format,t1/j1) ................... 1 44 5. 4 .6.1 synchronization procedure ............................... 1 4 5 5. 4 .7 summaryofframeconditions(t1/j1) ........................ 1 4 7 5.5 additionalfunctions(t1/j1) .................................. 1 48 5.5.1 errorperformancemonitoringandalarmhandling ............... 1 48
peb 2255 falc-lh v1.3 table of contents page data sheet 11 2000-07 5.5.2 auto modes . . ........................................... 150 5.5.3 error counter . ........................................... 150 5.5. 4 erroredsecond .......................................... 150 5.5.5 secondtimer ........................................... 150 5.5.6 clear channel capability . . . ................................ 151 5.5.7 in-band loop generation and detection . . ..................... 151 5.5. 8 transparentmode ........................................ 151 5.5. 9 pulsedensitydetection.................................... 152 5.6 testfunctions(t1/j1)....................................... 152 5.6.1 pseudo-random bit sequence generation and monitor . . ......... 152 5.6.2 remote loop . ........................................... 153 5.6.3 payload loop back . . ..................................... 15 4 5.6. 4 localloop .............................................. 155 5.6.5 single channel loop back (loopback of time slots) .............. 156 5.6.6 alarmsimulation(t1/j1) ................................... 157 6 operational description e1 .................................. 15 8 6.1 operationaloverviewe1..................................... 15 8 6.2 deviceresete1 ........................................... 15 8 6.3 deviceinitializationine1mode................................ 15 8 7 operational description t1/j1 ............................... 163 7.1 operationaloverviewt1/j1 .................................. 163 7.2 deviceresett1/j1 ......................................... 163 7.3 deviceinitializationint1/j1mode ............................. 163 8 signaling controller operating modes ........................ 16 9 8 .1 hdlcmode ............................................... 16 9 8 .1.1 non-auto-mode (mode.mds2...1 = 01) ....................... 16 9 8 .1.2 transparent mode 1 (mode.mds2...0 = 101) . . . ............... 16 9 8 .1.3 transparent mode 0 (mode.mds2...0 = 100) . . . ............... 170 8 .1. 4 receivedataflow........................................ 170 8 .1.5 transmitdataflow ....................................... 171 8 .2 extended transparent mode . . ................................ 171 8 .3 signalingcontrollerfunctions................................. 172 8 .3.1 sharedflags ............................................ 172 8 .3.2 preambletransmission .................................... 172 8 .3.3 transparenttransmissionandreception...................... 172 8 .3. 4 cyclictransmission(fullytransparent) ........................ 172 8 .3.5 crcon/offfeatures .................................... 173 8 .3.6 receiveaddresspushedtorfifo ........................... 173 8 .3.7 hdlcdatatransmission .................................. 173 8 .3. 8 hdlcdatareception ..................................... 175 8 .3. 9 sabitaccess(e1) ........................................ 176
peb 2255 falc-lh v1.3 table of contents page data sheet 12 2000-07 8 .3.10 bitorientedmessagemode(t1/j1) .......................... 176 8 .3.10.1 datalinkaccessinesf/f72format(t1/j1) ................. 17 8 9e1registers .............................................. 1 8 0 9 .1 e1controlregisteraddresses ................................ 1 8 0 9 .2 detaileddescriptionofe1controlregisters ..................... 1 8 3 9 .3 e1statusregisteraddresses................................. 22 8 9 . 4 detaileddescriptionofe1statusregisters ...................... 230 10 t1/j1 registers ........................................... 25 8 10.1 t1/j1controlregisteraddresses.............................. 25 8 10.2 detaileddescriptionoft1/j1controlregisters ................... 261 10.3 t1/j1statusregisteraddresses .............................. 307 10. 4 detaileddescriptionoft1/j1statusregisters .................... 30 9 11 electrical characteristics ................................... 335 11.1 absolutemaximumratings ................................... 335 11.2 operatingrange .......................................... 335 11.3 dccharacteristics.......................................... 336 11. 4 accharacteristics .......................................... 33 9 11. 4 .1 recommended osc illator circuits . . .......................... 33 9 11. 4 .2 x talclocktiming ....................................... 33 9 11. 4 .3 jtag boundary scan interface .............................. 3 4 1 11. 4 . 4 reset .................................................. 3 4 2 11. 4 .5 microprocessorinterface ................................... 3 4 2 11. 4 .5.1 intelbusinterfacemode ................................. 3 4 2 11. 4 .5.2 motorolabusinterfacemode.............................. 3 4 5 11. 4 .6 lineinterface ............................................ 3 4 7 11. 4 .7 systeminterface ......................................... 350 11. 4 . 8 pulsetemplates-transmitter............................... 355 11. 4 . 8 .1 pulsetemplatee1 ..................................... 355 11. 4 . 8 .2 pulsetemplatet1...................................... 356 11.5 capacitances .............................................. 357 11.6 packagecharacteristics ..................................... 35 8 11.7 testconfiguration .......................................... 35 9 12 package outlines .......................................... 360 13 appendix ................................................ 361 13.1 protectioncircuitry ......................................... 361 13.2 applicationnotes........................................... 362 13.3 software support ........................................... 362 13. 4 differences to version peb 2255 v1.1 .......................... 36 4 14 glossary ................................................. 365
peb 2255 falc-lh v1.3 list of figures page data sheet 13 2000-07 figure1 logicsymbol............................................ 21 figure2 multiplee1/t1/j1linkoverframerelay ...................... 22 figure 3 8 channel e1/t1/j1 interface to the atm layer . ................ 23 figure 4 multiplefalcclockingoptions ............................. 23 figure5 pinconfiguration......................................... 2 4 figure6 blockdiagram........................................... 4 6 figure 7 fifo word access (intel mode) . . ........................... 49 figure 8 fifowordaccess(motorolamode).......................... 50 figure 9 interruptstatusregisters .................................. 51 figure 10 block diagram of test access port and boundary scan . .......... 53 figure11 receiveclocksystem(e1)................................. 5 4 figure12 receiverconfiguration(e1)................................. 56 figure13 jitterattenuationperformance(e1)........................... 5 9 figure 1 4 jittertolerance(e1) ...................................... 60 figure15 transmitclocksystem(e1) ................................ 62 figure 16 the receive elastic buffer as circularly organized memory . . ..... 65 figure 17 2.0 48 mhzreceivesignalinghighway(e1).................... 6 8 figure 1 8 systeminterface(e1) ..................................... 70 figure 1 9 receivesysteminterfaceclocking(e1)....................... 71 figure 20 transmit system interface clocking: 2.0 48 mhz(e1)............. 7 4 figure 21 transmit system interface clocking: 8 .1 9 2mhz/ 4 .0 9 6mbit/s(e1)... 75 figure 22 2.0 48 mhztransmitsignalinghighway(e1) ................... 77 figure23 transmitterconfiguration(e1)............................... 7 9 figure 2 4 transmitlinemonitorconfiguration(e1) ...................... 8 1 figure25 dataflowintransparentmode.............................. 84 figure 26 crc 4 multiframealignmentrecoveryalgorithms ............... 9 2 figure 27 remote loop (e1) . . ...................................... 9 7 figure 2 8 payload loop (e1) . . ...................................... 98 figure 2 9 local loop (e1) .......................................... 99 figure 30 single channel loopback (e1) . . . .......................... 100 figure31 receiveclocksystem(t1/j1).............................. 102 figure32 receiverconfiguration(t1/j1) ............................. 10 4 figure33 jitterattenuationperformance(t1/j1) ....................... 107 figure 3 4 jittertolerance(t1/j1) ................................... 10 8 figure35 transmitclocksystem(t1/j1)............................. 110 figure 36 the receive elastic buffer as circularly organized memory . . .... 113 figure37 systeminterface(t1/j1).................................. 11 8 figure 3 8 receivesysteminterfaceclocking(t1/j1).................... 11 9 figure 3 9 2.0 48 mbit/sreceivesignalinghighway(t1/j1) ............... 120 figure 4 01.5 44 mbit/sreceivesignalinghighway(t1/j1) ............... 120 figure 4 1 receivefs/dlbitsintimeslot0onrdo(t1/j1).............. 122 figure 4 2 transmit system interface clocking: 1.5 44 mhz(t1/j1).......... 12 4
peb 2255 falc-lh v1.3 list of figures page data sheet 1 4 2000-07 figure 4 3 transmit system interface clocking: 8 mhz/ 4 mbit/s(t1/j1) ...... 125 figure 44 2.0 48 mbit/stransmitsignalingclocking(t1/j1)............... 126 figure 4 51.5 44 mbit/stransmitsignalinghighway(t1/j1)............... 126 figure 4 6 signalingmarkerforcas/cas-ccapplications(t1/j1).......... 127 figure 4 7 signalingmarkerforcas-brapplications(t1/j1).............. 12 8 figure 48 transmit fs/dl bits on x di(t1/j1) ......................... 12 9 figure 49 transmitterconfiguration(t1/j1) ........................... 13 4 figure50 transmitlinemonitorconfiguration(t1/j1)................... 136 figure 51 influences on synchronization status (t1/j1) . . . ............... 13 9 figure 52 remote loop (t1/j1) ..................................... 153 figure 53 payload loop (t1/j1) ..................................... 15 4 figure 5 4 local loop (t1/j1) . . ..................................... 155 figure 55 channel loopback (t1/j1). ................................ 156 figure56 hdlcreceivedataflowoffalc?-lh...................... 170 figure57 hdlctransmitdataflowoffalc?-lh ..................... 171 figure 5 8 interruptdrivendatatransmission(flowdiagram).............. 17 4 figure 5 9 interruptdriventransmissionexample....................... 175 figure60 interruptdrivenreceptionsequenceexample................. 175 figure61 crystaloscillatorcircuit(master/slavemode).................. 33 9 figure62 externaloscillatorcircuit(mastermode) ..................... 33 9 figure 63 x talexternalclocktiming ............................... 33 9 figure 6 4 externalpullablecrystaltuningrange ...................... 3 4 0 figure 65 jtag boundary scan timing .............................. 3 4 1 figure66 resettiming ........................................... 3 4 2 figure67 intelnon-multiplexedaddresstiming........................ 3 4 2 figure 6 8 intelmultiplexedaddresstiming............................ 3 4 3 figure 6 9 intelreadcycletiming................................... 3 4 3 figure70 intelwritecycletiming................................... 3 44 figure71 motorolareadcycletiming............................... 3 4 5 figure72 motorolawritecycletiming ............................... 3 4 6 figure73 timingofdualrailopticalinterface......................... 3 4 7 figure 7 4 receive clock and rfsp/free z stiming.................... 3 48 figure75 systeminterfacetiming .................................. 350 figure 76 x mfstiming........................................... 351 figure 77 x mfstiming(cont?d.).................................... 351 figure 7 8 systemclocktiming..................................... 353 figure 7 9 pulseshapeattransmitteroutputfore1applications........... 355 figure 8 0 t1pulseshape......................................... 356 figure 8 1 thermal behavior of package .............................. 35 8 figure 8 2 input/outputwaveformsforactesting ...................... 35 9 figure 8 3 protectioncircuitry....................................... 361 figure 84 externallinefrontendcalculator........................... 363
peb 2255 falc-lh v1.3 list of tables page data sheet 15 2000-07 table1 pindefinitions-microprocessorinterface...................... 25 table2 pindefinitions-lineinterface............................... 2 8 table 3 pin definitions - clock generation . ........................... 32 table 4 pindefinitions-systeminterface ............................ 35 table 5 pin definitions - miscellaneous . . . ........................... 4 3 table 6 data bus access (16-bit intel mode) .......................... 48 table 7 data bus access (16-bit motorola mode) ...................... 48 table 8 selectablebusandmicroprocessorinterfaceconfiguration........ 48 table 9 recommended receiver configuration values (e1) . . . .......... 56 table10 systemclocking(e1) ..................................... 5 9 table11 outputjitter(e1)......................................... 60 table12 receivebufferoperatingmodes(e1)......................... 6 4 table13 systemclockanddatarates(e1)........................... 6 9 table 1 4 timeslotassigner(e1).................................... 72 table15 transmitbufferoperatingmodes(e1) ........................ 7 8 table16 exampletransmitterconfigurationvalues(e1)................. 7 9 table 17 allocation of bits 1 to 8 oftimeslot0(e1)..................... 8 3 table 1 8 transmit transparent mode (doubleframe e1) . . ................ 84 table 1 9 crc-multiframe structure (e1) . . . ........................... 8 6 table20 transmittransparentmode(crcmultiframee1) ............... 8 7 table21 summaryofalarmdetectionandrelease(e1) ................. 9 3 table 22 recommended receiver configuration values (t1/j1). . ......... 10 4 table23 systemclocking(t1/j1) .................................. 106 table 2 4 outputjitter(t1/j1)...................................... 10 9 table25 receivebufferoperatingmodes(t1/j1) ..................... 112 table 26 channel translation modes (t1/j1) .......................... 113 table27 systemclockanddatarates(t1/j1)........................ 117 table 2 8 timeslotassigner(t1/j1) ................................ 121 table 2 9 transmitbufferoperatingmodes(t1/j1)..................... 132 table30 exampletransmitterconfigurationvalues(t1/j1).............. 13 4 table 31 pulse shaper programming (t1/j1) ......................... 135 table32 resynchronizationtiming(t1/j1)........................... 13 8 table 33 4 -framemultiframestructure(t1/j1)........................ 1 4 0 table 3 4 12-framemultiframestructure(t1/j1)....................... 1 4 1 table 35 extended superframe structure (f2 4 , esf ; t1/j1).............. 1 4 2 table36 72-framemultiframestructure(t1/j1)....................... 1 4 6 table37 summaryframerecover/outofframeconditions(t1/j1)....... 1 4 7 table 3 8 summaryofalarmdetectionandrelease(t1/j1).............. 1 48 table 3 9 initialvaluesafterreset(e1) .............................. 15 8 table 4 0 initializationparameters(e1)............................... 160 table 4 1 lineinterfaceinitialization(e1)............................. 161 table 4 2 framerinitialization(e1) .................................. 161
peb 2255 falc-lh v1.3 list of tables page data sheet 16 2000-07 table 4 3 hdlccontrollerinitialization(e1)........................... 162 table 44 cas-ccinitialization(e1)................................. 162 table 4 5 initial values after reset and fmr1.pmod = 1(t1/j1)........... 16 4 table 4 6 initializationparameters(t1/j1) ............................ 165 table 4 7 lineinterfaceinitialization(t1/j1)........................... 166 table 48 framerinitialization(t1/j1)................................ 166 table 49 initializationofthehdlccontroller(t1/j1).................... 167 table50 initializationofthecas-brcontroller(t1/j1).................. 16 8 table 51 e1 control register address arrangement .................... 1 8 0 table52 e1statusregisteraddressarrangement..................... 22 8 table 53 t1/j1 control register address arrangement . . . ............... 25 8 table 5 4 pulse shaper programming (t1/j1) ......................... 2 88 table55 t1/j1statusregisteraddressarrangement .................. 307 table56 maximumratings ....................................... 335 table 57 power supply range ..................................... 335 table 5 8 dcparameters ......................................... 336 table 5 9x taltimingparametervalues ............................ 33 9 table 60 jtag boundary scan timing parameter values. ............... 3 4 1 table61 resettimingparametervalues ............................ 3 4 2 table62 intelbusinterfacetimingparametervalues .................. 3 44 table63 motorolabusinterfacetimingparametervalues............... 3 4 6 table 6 4 dualrailopticalinterfaceparametervalues.................. 3 4 7 table 65 receive clock and rfsp/free z stimingparametervalues ..... 3 48 table66 systeminterfacetimingparametervalues ................... 351 table67 systemclocktimingparametervalues...................... 35 4 table 6 8 t1pulsetemplate(ansit1.102)........................... 356 table 6 9 capacitances........................................... 357 table70 packagecharacteristicvalues ............................. 35 8 table 71 ac test conditions . ..................................... 35 9
peb 2255 falc-lh v1.3 introduction data sheet 17 2000-07 1 introduction the falc ? -lh framer and line interface component is designed to fulfill all required interfacing between an analog e1/t1/j1 line and the digital pcm system highway, h.100 or h-mvip bus for world market telecommunication systems. due to its multitude of implemented functions, it fits to a wide range of networking applications and fulfills the according international standards. the falc ? -lh offers a generic e1/t1/j1 analog line interface without the need to change external components. optional crystal-less jitter attenuation reduces the amount of required external components. equipped with a flexible microprocessor interface, it connects to any control processor environment. a standard boundary scan interface is provided to support board level testing. flat pack device packaging, small number of external components and low power consumption lead to reduced overall system costs. other members of the falc ? family are the falc ? 5 4 for short haul applications, the falc ? 56 for long haul and short haul applications as well as the q uadfalc tm supplying four long haul and short haul interfaces on one single chip.
data sheet 1 8 2000-07 type package peb 2255 p-m q fp- 8 0-1 e1/t1/j1 framer and line interface component for long and short haul applications falc ? -lh peb 2255 version 1.3 1.1 features line interface high density, generic interface for all e1/t1/j1 applications analog receive and transmit circuitry for long haul and short haul applications data and clock recovery using an integrated digital phase locked loop maximum line attenuation up to - 4 3dbat102 4 khz (e1) and up to -36 db at 772 khz (t1/j1) programmable transmit pulse shapes for e1 and t1/j1 pulse masks programmable line build-out for cs u signals according to ansi t1. 4 03 + fcc6 8 in steps of 0 db, -7.5 db, -15 db and -22.5 db (t1/j1) low transmitter output impedances for high transmit return loss tristate function of the analog transmit line outputs transmit line monitor protecting the device from damage jitter specifications of it u -t i. 4 31, g.703, g.736 (e1), g. 8 23 (e1) and at & t tr62 4 11 (t1/j1) are met optional crystal-less wander and jitter attenuation/compensation dual rail or single rail digital inputs and outputs u nipolar nr z or cmi coding for interfacing fibre optical transmission routes selectable line codes (e1: hdb3, ami - t1/j1: b 8z s, ami with z cs) for analog interface loss of signal indication with programmable thresholds according to it u -t g.775 and ets300233 (e1)/ansi t1. 4 03, t1.231(t1/j1) clock generator for jitter free system/transmit clocks local loop and remote loop for diagnostic purposes only one type of transformer (ratio 1: ) for e1 75/120 ? and t1/j1 100/110 ? 2 p-mqfp-80-1
peb 2255 falc-lh v1.3 introduction data sheet 1 9 2000-07 frame aligner frame alignment/synthesis for 20 48 kbit/s according to it u -t g.70 4 (e1) and for 15 44 kbit/saccordingtoit u -t g.70 4 and jt g.70 4 (t1/j1) programmable frame formats : e1: doubleframe, crc multiframe (e1) t1: 4 -frame multiframe (f 4 ,ft), 12-frame multiframe (f12, d3/ 4 ), extended superframe (f2 4 , esf), remote switch mode (f72, slc 9 6) selectable conditions for recover/loss of frame alignment crc 4 to non-crc 4 interworking of it u -t g. 706 annex b (e1) error checking via crc 4 procedures according to it u -t g. 706 (e1) error checking via crc6 procedures according to it u -t g. 706 and jt g.706 (t1/j1) performs synchronization in esf format according to ntt requirements (j1) alarm and performance monitoring per second 16 bit counter for crc-, framing errors, code violations, error monitoring via e bit and sa6 bit (e1), errored blocks, prbs bit errors insertion and extraction of alarm indication signals (ais, remote ? y ellow alarm, a ux p) idle code insertion for selectable channels 8 .1 9 2 mhz/2.0 48 mhz (e1) or 8 .1 9 2 mhz/1.5 44 mhz (t1/j1) system clock frequency selectable 20 48 / 4 0 9 6 kbit/s backplane interface with programmable receive/transmit timeslot offset programmable tristate function of 4 0 9 6 kbit/s output via rdo elastic store for receive and transmit route clock wander and jitter compensation ; controlled slip capability and slip indication programmable elastic buffer size: 2 frames/1 frame/short buffer/bypass supports fractional e1 or t1 access flexible transparent modes programmable in-band loop code detection and generation (tr62 4 11) channel loop back, line loop back or payload loop back capabilities (tr5 4 016) pseudo random bit sequence (prbs) generator and monitor provides loop-timed mode clear channel capabilities (t1/j1) signaling controller hdlc controller bit stuffing, crc check and generation, flag generation, flag and address recognition, handling of bit oriented functions, programmable preamble dl-channel protocol for esf format according to ansi t1. 4 03 or according to at & t tr5 4 016 (t1/j1) dl-channel protocol for f72 (slc 9 6) format cas controller with last look capability, enhanced cas- register access and freeze signaling indication robbed bit signaling capability (t1/j1)
peb 2255 falc-lh v1.3 introduction data sheet 20 2000-07 provides access to serial signaling data streams cas multiframe synchronization and synthesis according to it u -t g.732 alarm insertion and detection (ais and los in timeslot 16) transparent mode fifo buffers (6 4 bytes deep) for efficient transfer of data packets. time-slot assignment any combination of time slots selectable for data transfer independent of signaling mode microprocessor interface 8 /16 bit microprocessor bus interface (intel or motorola type) all registers directly accessible (byte or word access) multiplexed and non-multiplexed address bus operations extended interrupt capabilities hardware and software reset one second timer general boundary scan standard ieee 11 49 .1 p-m q fp- 8 0 package ; body size 1 4 x1 4; pitch 0.65 5v power supply typical power consumption 4 50 mw applications wireless basestations e1/t1/j1 atm gateways, multiplexer e1/t1/j1 channel & data service u nits (cs u ,ds u ) e1/t1/j1 internet access equipment lan/wan router isdn pri, pab x digital access cross connect systems (dacs) sonet/sdh add/drop multiplexer
peb 2255 falc-lh v1.3 introduction data sheet 21 2000-07 1.2 logic symbol figure 1 logic symbol falc ? -lh peb 2255 scl k r s y pr/rfm rsigm rmfb dlr/rsig rdo res roid rl1 / rdip / roid rl2 / rdin / rcl k i refr v ddr v ssr tdi tms tc k tdo v dd v ss a(0-6) d(0-15) ale rd/ds wr/rw bhe/ble dbw cs im int x sig x sigm x mfb dl x x di x mfs scl kx s y p x x l1m x l1 / x dop / x oid x l2 / x don x l2m x oid x cl k /fsc v dd x v ss x microprocessor interface transmit system interface receive system interface transmit line interface boundary scan receive line interface rfsp rcl k x tal1 x tal2 x tal3 x tal 4 s y nc s y nc2 cl k 16m cl k 12m cl k8 m cl kx fsc system clocks f0044
peb 2255 falc-lh v1.3 introduction data sheet 22 2000-07 1.3 typical applications the figures show a multiple link circuit for frame relay applications using the falc-lh together with the 12 8 channel hdlc controller m12 8x and the memory timeswitch mtls as well as an 8 channel interface to the atm layer combined with n iwe 8 device. figure 2 multiple e1/t1/j1 link over frame relay mtsl peb 20 4 7 memory time switch falc ? -lh peb 2255 falc ? -lh peb 2255 falc ? -lh peb 2255 falc ? -lh peb 2255 e1 / t1 / j1 e1 / t1 / j1 e1 / t1 / j1 e1 / t1 / j1 m u nich12 8x peb 2032 4 cp u memory system bus pci/generic clock clock clock(s) f0024
peb 2255 falc-lh v1.3 introduction data sheet 23 2000-07 figure 3 8 channel e1/t1/j1 interface to the atm layer figure 4 multiple falc clocking options iwe 8 p x b 4 220 falc ? -lh peb 2255 falc ? -lh peb 2255 e1 / t1 / j1 e1 / t1 / j1 ram atm layer port 1 port 8 aal1 or atm mode f0026 falc ? -lh peb 2255 falc ? -lh peb 2255 falc ? -lh peb 2255 falc ? -lh peb 2255 clock(s) falc ? -lh peb 2255 falc ? -lh peb 2255 falc ? -lh peb 2255 falc ? -lh peb 2255 falc ? -lh peb 2255 falc ? -lh peb 2255 falc ? -lh peb 2255 falc ? -lh peb 2255 clock(s) pullable crystals f0045
peb 2255 falc-lh v1.3 pin descriptions data sheet 2 4 2000-07 2 pin descriptions 2.1 pin diagram (top view) figure 5 pin configuration itp10482 tms v ddr ss v sync xsigm rsigm rd0 int res bhe/ble cs wr/rw rd/ds ale a6 a5 a4 a3 a2 a1 a0 d0 tck xl1m tdi ddx v xl1/xdop/xoid ssx v xtal3 dbw xl2/xdon xl2m im xtal4 xtal1 xtal2 rl1/rdip/roid refr rl2/rdin/rclki ssr v v dd xdi dd v v ss peb 2255 falc -lh d1 d2 d3 dd v v ss d6 d5 d4 d7 d8 d9 d11 d10 d12 d13 d15 d14 td0 1234567891011121314151617181920 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 41 xmfs sclkx sclkr sypx /rfm fsc rmfb /xoid dlx dlr/rsig freezs/rfsp rclk 16m 12m 8m clkx fsc/xclk xsig/sync2/roid clk clk clk r sypr xmfb p-mqfp-80-1
peb 2255 falc-lh v1.3 pin descriptions data sheet 25 2000-07 2.2 pin definitions and functions table 1 pin definitions - microprocessor interface pin no. symbol input (i) output (o) supply (s) function 4 2... 48 a0 ? a6 i address bus these inputs interface to seven bits of the system?s address bus to select one of the internal registers for read or write. 4 1?3 8 35?2 8 25?22 d0?d3 d 4 ?d11 d12..d15 i/o data bus bidirectional tristate data lines which interface to the system?s data bus. their configuration is controlled by the level of pin dbw: 8 -bit mode (dbw = 0): d0 ? d7 are active. d 8 ? d15 are in high impedance and have to be connected to v dd or v ss . 16-bit mode (dbw = 1): d0 ? d15 are active. in case of byte transfers, the active half of the bus is determined by a0 and bhe /ble and the selected bus interface mode (via pin im). the unused half is in high impedance state. 49 ale i address latch enable a high on this line indicates an address on the external address/data bus. the address information provided on lines a0 ? a6 is internally latched with the falling edge of ale. this function allows the falc ? -lh to be connected to a multiplexed address/data bus directly. in this case, pins a0 ? a6 must be connected to the data bus pins externally. in case of demultiplexed mode this pin has to be connected to v dd or v ss directly. 52 cs i chip select a low signal selects the falc ? -lh for read and write operations.
peb 2255 falc-lh v1.3 pin descriptions data sheet 26 2000-07 50 rd /ds i read enable (intel bus mode) this signal indicates a read operation. when the falc ? -lh is selected via cs ,therd signal enables the bus drivers to output data from an internal register addressed by a0?a6ontothedatabus. data strobe (motorola bus mode) this pin serves as input to control read/write operations. it is logically ored with pin cs . 51 wr /rw i write enable (intel bus mode) this signal indicates a write operation. when cs is active the falc ? -lh loads an internal register with data provided on the data bus. read/write enable (motorola bus mode) this signal distinguishes between read and write operation. 11 dbw i data bus width (bus interface mode) a low signal on this input selects the 8 -bit bus interface mode. a high signal on this input selects the 16-bit bus interface mode. in this case word transfer to/from the internal registers is enabled. byte transfers are implemented by using a0 and bhe /ble . 8 im i interface mode the level at this pin defines the bus interface mode: a low signal on this input selects the intel interface mode. a high signal on this input selects the motorola interface mode. table 1 pin definitions - microprocessor interface (cont?d) pin no. symbol input (i) output (o) supply (s) function
peb 2255 falc-lh v1.3 pin descriptions data sheet 27 2000-07 53 bhe /ble i + p u bus high enable (intel bus mode) if 16-bit bus interface mode is enabled, this signal indicates a data transfer on the upper byte of the data bus (d 8 ? d15). in 8 -bit bus interface mode this signal has no function and should be tied to v dd . bus low enable (motorola bus mode) if 16-bit bus interface mode is enabled, this signal indicates a data transfer on the lower byte of the data bus (d0 ? d7). in 8 -bit bus interface mode this signal has no function and should be tied to v dd . 56 int o/od interrupt request int serves as general interrupt request which may include all interrupt sources. these interrupt sources can be masked via registers imr0 ? 5. interrupt status is reported via registers gis (global interrupt status) and isr0 ? 3,5. output characteristics (push-pull active low/ high, open drain) are determined by programming the ipc register. (od = open drain output) table 1 pin definitions - microprocessor interface (cont?d) pin no. symbol input (i) output (o) supply (s) function
peb 2255 falc-lh v1.3 pin descriptions data sheet 2 8 2000-07 table 2 pin definitions - line interface pin no. symbol input (i) output (o) supply (s) function line interface receive 2 rl1 i (analog) line receiver 1 analog input from the external transformer. selected if lim1.drs = 0. rdip i receive data input positive digital input for received dual rail pcm( + ) route signal which will be latched with the internal generated receive route clock. an internal dpll will extract the receive route clock from the incoming data pulse. the duty cycle of the received signal has to be close to 50 % . the dual rail mode is selected if lim1.drs = 1 and fmr0.rc1 = 1. input polarity is selected by bit rc0.rdis (after reset: active low). roid i receive optical interface data u nipolar data received from fiber optical interface with 20 48 kbit/s (e1) or 15 44 kbit/s (t1/ j1). latching of data is done with the falling edge of rcl k i. input polarity is selected by bit rc0.rdis. the single rail mode is selected if lim1.drs = 1 and fmr0.rc1 = 0. 8 0roidi receive optical interface data loop.spn = 1 u nipolar data received from fiber optical interface with 20 48 kbit/s (e1) or 15 44 kbit/s (t1/ j1). latching of data is done with the falling edge of rcl k i. input polarity is selected by bit rc0.rdis. the single rail mode is selected if lim1.drs = 1 and fmr0.rc1 = 0. note: this pin contains multiple functions, see also sync2 and xsig.
peb 2255 falc-lh v1.3 pin descriptions data sheet 2 9 2000-07 4 rl2 i (analog) line receiver 2 analog input from the external transformer. selected if lim1.drs = 0. rdin i receive data input negative input for received dual rail pcm(-) route signal which will be latched with the internal generated receive route clock. an internal dpll will extract the receive route clock from the incoming data pulse. the duty cycle of the received signal has to be close to 50 % . the dual rail mode is selected if lim1.drs = 1 and fmr0.rc1 = 1. input polarity is selected by bit rc0.rdis (after reset: active low). rcl k ii receive clock input receive clock input for the optical interface if lim1.drs = 1 and fmr0.rc1/0 = 00. clock frequency: 20 48 khz(e1)or15 44 khz (t1/j1). table 2 pin definitions - line interface (cont?d) pin no. symbol input (i) output (o) supply (s) function
peb 2255 falc-lh v1.3 pin descriptions data sheet 30 2000-07 line interface transmit 15 x l1 o (analog) transmit line 1 analog output to the external transformer. selected if lim1.drs = 0. after reset this pin is in a high impedance state until bit fmr0. x c1 is set. x dop o transmit data output positive this digital output for transmitted dual rail pcm( + ) route signals can provide - half bauded signals with 50 % duty cycle (lim0. x fb = 0) or - full bauded signals with 100 % duty cycle (lim0. x fb = 1) thedatawillbeclockedoffonthepositive transitions of x cl k in both cases. output polarity is selected by bit lim0. x dos (after reset: active low). the dual rail mode is selected if lim1.drs = 1andfmr0. x c1 = 1. after reset this pin is in a high impedance state until register lim1.drs is set. x oid o transmit optical interface data u nipolar data sent to fiber optical interface with 20 48 kbit/s (e1) or 15 44 kbit/s (t1/j1) which will be clocked off on the positive transitions of x cl k .clockingoffdatainnr z code is done with 100 % duty cycle. data in cmi code (e1 only) are shifted out with 50 % or 100 % duty cycle according to the cmi coding. output polarity is selected by bit lim0. x dos (after reset: data is sent active high). the single rail mode is selected if lim1.drs = 1 and fmr0. x c1 = 0. after reset this pin is in a high impedance state until register lim1.drs is set. if loop.spn = 1 this pin function is not defined and should be tristated by enabling x pm2. x lt. table 2 pin definitions - line interface (cont?d) pin no. symbol input (i) output (o) supply (s) function
peb 2255 falc-lh v1.3 pin descriptions data sheet 31 2000-07 17 x l1m i transmit line 1 monitor analog input from external transmit transformer ( x l1). this pin must be connected, otherwise pin x l1 could be set into high impedance state automatically. if digital line interface mode is selected (lim1.drs = 1), this input has to be connected to v ss x . 13 x l2 o (analog) transmit line 2 analog output for the external transformer. selected if lim1.drs = 0. after reset this pin is in a high impedance state until bit fmr0. x c1 is set. x don o transmit data output negative this digital output for transmitted dual rail pcm(-) route signals can provide - half bauded signals with 50 % duty cycle (lim0. x fb = 0) or - full bauded signals with 100 % duty cycle (lim0. x fb = 1) thedatawillbeclockedoffonthepositive transitions of x cl k in both cases. output polarity is selected by bit lim0. x dos (after reset: active low). the dual rail mode is selected if lim1.drs = 1 and fmr0. x c1 = 1. after reset this pin is in a high impedance state until register lim1.drs is set. 12 x l2m i transmit line 2 monitor analog input from external transmit transformer ( x l2). this pin must be connected, otherwise pin x l2 could be set into high impedance state automatically. if digital line interface mode is selected (lim1.drs = 1), this input has to be connected to v ss x . table 2 pin definitions - line interface (cont?d) pin no. symbol input (i) output (o) supply (s) function
peb 2255 falc-lh v1.3 pin descriptions data sheet 32 2000-07 table 3 pin definitions - clock generation pin no. symbol input (i) output (o) supply (s) function 7 x tal1 i crystal connection 16.384 mhz a pullable crystal of 16.3 84 mhz has to be provided at these pins, if jitter attenuation of the system clocks is done internally. if not, or if crystal-less jitter attenuation is used, either a regular crystal of 16.3 84 mhz has to be connected to x tal1/ x tal2 or a 16.3 84 -mhz clock must be connected to x tal1 while x tal2 is left open. 6 x tal2 o 10 x tal3 i crystal connection 16.384 mhz (e1)/12.352 mhz (t1/j1) a pullable crystal of 16.3 84 mhz/12.352 mhz is only required at these pins, if jitter attenuation of the transmit clocks is done internally. if jitter attenuation is provided externally, the jitter attenuated clock of 16.3 84 mhz/12.352 mhz has to be applied to x tal3 while x tal 4 is left open. if crystal-less jitter attenuation is used, either a regular crystal of16.3 84 mhz/12.352 mhz has to be connected to x tal3/ x tal 4 or a 16.3 84 - mhz/12.352-mhz clock has to be connected to x tal3 while x tal 4 is left open. e1 mode only: if no transmit jitter attenuation is required, x tal3 should be connected to v dd or v ss , x tal 4 is to be left open. 9x tal 4 o 7 9x cl k o transmit clock transmit clock of 2.0 48 mhz (e1) or 1.5 44 mhz (t1/j1). this clock is driven from scl kx or rcl k or generated internally. fsc o 8 khz frame synchronization pulse is output on this pin, if lim1.efsc = 1is selected. the synchronization pulse is active high for one cycle (pulse width = 488 ns) and derived from the clock supplied on pin cl k 16m.
peb 2255 falc-lh v1.3 pin descriptions data sheet 33 2000-07 66 fsc o 8 khz frame synchronization pulse is output on this pin. the synchronization pulse is active low for one cycle (pulse width =488 ns) and derived from the clock supplied on pin cl k 16m. 75 cl k 16m o system clock 16.384 mhz buffered x tal1 clock (lim3.csc = 1) or jitter attenuated clock (lim3.csc = 0, if crystal-less jitter attenuation is used). 76 cl k 12m o system clock 16.384 mhz (e1)/12.384 mhz (t1/j1) buffered x tal3 clock (lim3.csc = 1) or jitter attenuated clock (lim3.csc = 0, if crystal-less jitter attenuation is used). 77 cl k8 mo system clock 8.192 mhz clock derived from cl k 16m reference. 7 8 cl kx o system clock output output frequencies are 2.0 48 mhz or 4 .0 9 6 mhz, inverted or non-inverted. the clock is derived from cl k 16m, frequency and polarity in relation to fsc are selected by setting of lim0.scl1...0. 60 s y nc i clock synchronization if a clock is detected at the s y nc pin, the falc ? -lh synchronizes to this 2.0 48 -mhz (e1)/ 2.0 48 or 1.5 44 -mhz (t1/j1) clock if in master mode or if signal is lost in slave mode. this pin hastobeconnectedtov ss ,ifnoclockis supplied. table 3 pin definitions - clock generation (cont?d) pin no. symbol input (i) output (o) supply (s) function
peb 2255 falc-lh v1.3 pin descriptions data sheet 3 4 2000-07 8 0s y nc2 i clock synchronization 2 secondary reference clock for internal transmit clock generation. the clock frequency is 2.0 48 -mhz (e1) or 2.0 48 / 1.5 44 -mhz (t1/j1). this function is selected by setting lim3.es y= 1 note: this pin contains multiple functions, see also roid and xsig. 72 rcl k o + p u receive clock extracted from the incoming data pulses. clock frequency: 20 48 khz (e1) or 15 44 khz (t1/j1) in case of loss of signal (los) the rcl k is derived from the clock that is provided on x tal1. if lim0.elos is set, rcl k issethighincaseof loss of signal (frs0.los = 1). if nr z mode is selected, rcl k is the buffered rcl k i clock. table 3 pin definitions - clock generation (cont?d) pin no. symbol input (i) output (o) supply (s) function
peb 2255 falc-lh v1.3 pin descriptions data sheet 35 2000-07 table 4 pin definitions - system interface pin no. symbol input (i) output (o) supply (s) function system interface receive 57 rdo o receivedataout received data which is sent to the system highway at 4 0 9 6kbit/s,20 48 kbit/s or 15 44 kbit/ s (t1/j1 only). in 4 0 9 6 kbit/s mode data is shifted out in the channel phase which is selected by rc0.sics. during the other channel phase rdo is set into tristate. clocking off data is done with the fa lling edge of scl k r or rcl k , if the receive elastic store is bypassed. the delay between the beginning of time-slot 0 and the initial edge of scl k r(after s y pr goes active) is determined by the values of registers rc1 and rc0. 70 dlr o data link bit receive e1 mode : marks the s a 4 ... 8 bits within the data steam on rdo. the s a 4 ... 8 bit positions in time slot 0 of every frame not containing the frame alignment signal are selected by register x c0.sa 4 e- sa 8 e. t1/j1 mode : provides a signal which marks the dl bit position within the data stream on rdo. it can be used as receive strobe signal for external data link controllers. in 4 0 9 6kbit/smodedlris active only during the channel phase selected by rco.sics. rsig o receive signaling data output for receive signaling data sent to the signaling highway. this function is selected by setting loop.spn = 1 lim3.es y= 1 x sp.casen = 0
peb 2255 falc-lh v1.3 pin descriptions data sheet 36 2000-07 71 rfsp o receive frame synchronous pulse e1: fmr3.cfr z= 0 t1/j1: x c0.sfr z= 0 active low framing pulse derived from the received pcm route signal. during loss of synchronization (bit frs0.lfa) this pulse is suppressed (not influenced during alarm simulation). the pulse frequency is 8 khz, pulse width is 488 ns (e1) or 6 48 ns (t1/j1). o prbs monitor status the status of the prbs monitor is output on this pin, if fmr3.cfr z= 0(e1)or x c0.sfr z= 1 (t1/j1) and lcr1.eprm = 1. it is set high, if the prbs monitor is in synchronous state. free z so freeze signaling (t1/j1) if x c0.sfr z= 1 (t1/j1) or fmr3.cfr z= 1 (e1) and lcr1.eprm = 0, the freeze signaling status is indicated. register access (loop.spn = 0 and lim3.es y= 0): e1: bit frs1.tsl16lfa = 1 t1: frs0.lfa/lmfa = 1 or a receive slip (positive or negative) occurred serial signaling access (loop.spn = 1 and lim3.es y= 1): e1: bit frs1.tsl16lfa = 1 or frs0.los = 1 or a receive slip occurred t1: frs0.lfa/lmfa = 1 or frs0.los = 1 or a receive slip occurred the signal is cleared after an error-free superframe. during alarm simulation this signal gets active during simulation steps 2 and 6. table 4 pin definitions - system interface (cont?d) pin no. symbol input (i) output (o) supply (s) function
peb 2255 falc-lh v1.3 pin descriptions data sheet 37 2000-07 65 s y pr i synchronous pulse receive sic2.srfso = 0 (reset value): defines the beginning of time slot 0 on system highway port rdo together with the values of rc0.rco, rc0.rcos and rc1.rto. sampling is done with the falling edge of scl k r. the pulse cycle is an integer multiple of 125 s. rfm o receive frame marker sic2.srfso = 1: this marker will be active high for one 2.0 48 - mhz (e1)/1.5 44 -mhz (t1/j1) cycle (sic1.srsc = 1 ; 2.0 48 mbit/s pcm highway interface mode) or two 8 .1 9 2-mhz cycles (sic1.srsc = 0 ; 4 .0 9 6 mbit/s pcm highway interface mode). it is clocked with the falling edge of scl k rorrcl k , depending on the selected receive buffer size (sic1).the marker can be activated within any bit position of a received frame (rc0/1). 63 scl k ri system clock receive working clock for the receive system interface with a frequency of 8 .1 9 2 mhz (sic1.srsc = 0, sic1.s x sc = 0) or 2.0 48 mhz (e1)/1.5 44 mhz (t1/j1) (sic1.srsc = 1, sic1.s x sc = 1).ifthe receive elastic store is bypassed (sic1.rbs1...0), the clock supplied on this pin is ignored. during reset phase, a clock has to be provided. table 4 pin definitions - system interface (cont?d) pin no. symbol input (i) output (o) supply (s) function
peb 2255 falc-lh v1.3 pin descriptions data sheet 3 8 2000-07 5 8 rsigm o receive signaling marker e1/t1/j1 mode : marks the time-slots which are defined by register rtr1- 4 of every received frame on port rdo. t1/j1 cas-br mode : when using the cas-br signaling scheme, the robbed bit of each channel every six frames is marked, if it is enabled via register x c0.brm = 1. general :in 4 0 9 6 kbit/s mode rsigm is active only during the channel phase selected by rco.sics. 67 rmfb o receive multiframe begin rmfb marks the beginning of every received multiframe (rdo, first bit of the fas word in frame 1 of a multiframe). active high for one 20 48 kbit/s period. in 4 0 9 6 kbit/s mode rmfb is active during the first two bits of channel phase one of a multiframe. in t1/j1 mode the function depends on programming bit x c0.mfbs: mfbs = 1: rmfb marks the beginning of every received multiframe (rdo). mfbs = 0: marks the beginning of every received superframe. additional pulses every 12 frames are provided when using esf/f2 4 or f72 format. table 4 pin definitions - system interface (cont?d) pin no. symbol input (i) output (o) supply (s) function
peb 2255 falc-lh v1.3 pin descriptions data sheet 3 9 2000-07 system interface transmit 6 8x mfb o transmit multiframe begin e1 mode/loop.spn = 0 : marks the begin of every transmitted multiframe ( x di). t1/j1 mode/ x c0.mfbs = 1 : x mfb marks the beginning of every transmitted multiframe ( x di). t1/j1 mode/ x c0.mfbs = 0 : x mfb marks the beginning of every transmitted superframe. additional pulses every 12 frames are provided when using esf/f2 4 or f72 format. general: this signal is always active high for one 20 48 kbit/s period. in 4 0 9 6kbit/smode,itisactive during the first two bits of a multiframe. x oid o transmit optical interface data e1 mode only/loop.spn = 1 : u nipolar data sent to fiber optical interface with 20 48 kbit/s which will be clocked off on the positive transitions of x cl k . clocking off data in nr z mode is done with a duty cycle of 100 % . cmi code data is shifted out with a duty cycle of 50 % /100 % according to the cmi coding. output polarity is selected by lim0. x dos (active high after reset). single rail mode is selected if lim1.drs = 1 and fmr0. x c1 = 0. table 4 pin definitions - system interface (cont?d) pin no. symbol input (i) output (o) supply (s) function
peb 2255 falc-lh v1.3 pin descriptions data sheet 4 0 2000-07 6 4 s y p x i synchronous pulse transmit defines the beginning of time slot 0 at system highway port x di together with the values of x c0. x co, x c1. x to and x c1. x cos. sampling is done with the falling edge of scl kx . the pulse cycle is an integer multiple of 125 s. 62 scl kx i system clock transmit working clock for the transmit system interface with a frequency of 8 .1 9 2mhz(sic1.s x sc = 0, sic1.srsc = 0) or 2.0 48 mhz (e1)/1.5 44 mhz (t1/j1) (sic1.s x sc = 1, sic1.srsc = 1). 55 x di i transmit data in transmit data received from the system highway. latching of data is done with the falling transitions of scl kx . e1 data rate (scl kx = 8 .1 9 2mhz): fmr1.imod = 0: 4 0 9 6kbit/s fmr1.imod = 1: 20 48 kbit/s e1 data rate (scl kx = 2.0 48 mhz): fmr1.imod = 1 & sic1.s x sc = 1: 20 48 kbit/s t1/j1data rate (scl kx = 8 .1 9 2mhz): fmr1.imod = 0: 4 0 9 6kbit/s fmr1.imod = 1 & sic1.s x sc = 0: 20 48 kbit/s t1/j1data rate (scl kx = 1.5 44 mhz): fmr1.imod = 1 & sic1.s x sc = 1: 15 44 kbit/s the delay between the beginning of time slot 0 and the initial edge of scl kx (after s y p x goes active) is determined by the values of transmit time slot offset ( x c1. x to5-0), transmit clock slot offset ( x c0. x co2-0) and x c1. x cos. table 4 pin definitions - system interface (cont?d) pin no. symbol input (i) output (o) supply (s) function
peb 2255 falc-lh v1.3 pin descriptions data sheet 4 1 2000-07 6 9 dl x o data link bit transmit e1 mode :marksthes a 4 ... 8 bits within the data stream on x di. the s a 4 ... 8 bit positions in time- slot 0 of every frame not containing the frame alignment signal are selected by register x c0.sa 4 e-sa 8 e. t1/j1 mode : this output provides a signal which marks the dl-bit position within the data stream on x di. in 4 0 9 6 kbit/s mode dl x is active only during the channel phase selected by rco.sics. 8 0 x sig i transmit signaling data input for transmit signaling data received from the signaling highway. this function is selected by setting loop.spn = 1 lim3.es y= 1 note: this pin contains multiple functions, see also sync2 and roid. table 4 pin definitions - system interface (cont?d) pin no. symbol input (i) output (o) supply (s) function
peb 2255 falc-lh v1.3 pin descriptions data sheet 4 2 2000-07 5 9x sigm o transmit signaling marker marks the transmit time slots which are defined by register ttr1- 4 of every frame transmitted on port x di. in 4 0 9 6 kbit/s mode, x sigm is active only during the channel phase which is selected by rc0.sics. t1 mode/cas-br: if cas-br is selected by fmr1.sigm = 1, the robbed bit of each channel every six frames is marked, if marker is enabled by setting x c0.brm = 1. 61 x mfs i transmit multiframe synchronization this port defines the first frame of the multiframe on the transmit system interface port x di. note: a new multiframe position has been settled at least one multiframe after pulse x mfs has been supplied. if this input is not used, it has to be connected to v ss . in this case multiframe start is generated internally. table 4 pin definitions - system interface (cont?d) pin no. symbol input (i) output (o) supply (s) function
peb 2255 falc-lh v1.3 pin descriptions data sheet 4 3 2000-07 table 5 pin definitions - miscellaneous pin no. symbol input (i) output (o) supply (s) function power supply 1 v ddr s positive power supply for the analog receiver 5 v ssr s power supply: ground for the analog receiver 16 v dd x s positive power supply for the analog transmitter 1 4 v ss x s power supply: ground for the analog transmitter 27, 37, 7 4 v ss s power supply: ground for digital subcircuits (0 v) for correct operation, all three pins have to be connected to ground. 26, 36, 73 v dd s positive power supply for the digital subcircuits (5.0 v) for correct operation, all three pins have to be connected to positive power supply. device reset 5 4 res i reset a high signal on this pin forces the falc ? -lh into reset state. during reset the falc ? -lh needs active clocks on pins scl k r, scl kx , x tal1 and x tal3 (e1: x tal3 only, if slicer mode selectable by lim1.jatt/rl = 10 will be used). during reset - all unidirectional output stages are in high- impedance state, except pins cl k 16m, cl k 12m, cl k8 m, cl kx ,fsc , x cl k and rcl k (active clocks are required during reset on pins scl k r, scl kx , x tal1 and x tal3 1) ) - all bidirectional output stages (data bus) are in input mode if signal rd is ?high?
peb 2255 falc-lh v1.3 pin descriptions data sheet 44 2000-07 note: unused input pins have to be connected to a defined voltage level (v dd or v ss ). analog reference 3refro reference resistance of 12 k ? + /- 1 % and a capacitor of 6 8 0 pf (including external parasitic capacitances). both have to be connected to pin v ssr in parallel by short external connections. boundary scan/joint test access group (jtag) 2) 1 8 tdi i + p u test data input for boundary scan according to ieee std. 11 49 .1 if not connected an internal pull-up transistor ensures high input level. 1 9 tms i + p u test mode select for boundary scan if not connected an internal pull-up transistor ensures high input level. 20 tc k i + p u test clock for boundary scan if not connected an internal pull-up transistor ensures high input level. 21 tdo o test data output for boundary scan 1) x tal3 not required in e1/bypass mode 2) boundary scan reset is done automatically upon power up. no pin trs is provided. table 5 pin definitions - miscellaneous (cont?d) pin no. symbol input (i) output (o) supply (s) function
peb 2255 falc-lh v1.3 functional description e1/t1/j1 data sheet 4 5 2000-07 3 functional description e1/t1/j1 3.1 functional overview the falc ? -lh device contains analog and digital function blocks, which are configured and controlled by an external microprocessor or microcontroller. the main interfaces are receive and transmit line interface pcm system highway interface microprocessor interface boundary scan interface as well as several control lines for reset and clocking purpose. the main internal functional blocks are analog line receiver with equalizer network and digital clock/data recovery analog line driver with programmable pulse shaper clock generation elastic buffers for receive and transmit direction receive framer receive line decoding, alarm detection, and prbs monitoring transmit framer transmit line coding, alarm and prbs generation receive jitter attenuator transmit jitter attenuator hdlc controller loop switching (local, remote, payload, single channel) register access interface boundary scan control
peb 2255 falc-lh v1.3 functional description e1/t1/j1 data sheet 4 6 2000-07 3.2 block diagram figure 6 block diagram local loop equalizer + filter analog los detector alarm detector pulse shaper + transmit attenuation jatt receive elastic buffer backplane interface transmit elastic buffer pay- load loop divider divider pd osc. dco- x divider pd osc. dco-r alignment performance monitoring counters framer dl extract sa 4 - 8 extract clock & data recovery dpll backplane interface peak detector hdlc dl/bom sa 4 - 8 time slot assigner cas-cc cas-br signaling controller ami b 8z s hdb3 encoder prbs generator generation framer dl insert sa 4 - 8 insert ami b 8z s hdb3 decoder prbs monitor boundary scan microprocessor interface interrupt control scl kx x tal3 12.352 mhz (t1) 16.3 84 mhz (e1) system clocks x tal1 16.3 84 mhz s y nc int control d0 ... 15 a0 ... 6 x cl k x l1 / x l2 x dop / x don x oid / --- rcl k rfsp scl k r s y pr rdo rmfb rsigm dlr / rsig dl x x sigm x mfb x di x sig s y p x x mfs scl kx rcl k s y nc2 rcl k roid rl1 / rl2 rdip / rdin roid / rcl k i dr dr line driver x s e1 t1 or rl (t1) rl (e1) rl (e1) rl (t1) 8 mhz 2 mhz 2/1.5mhz 8 /6mhz cl k 12m f0046
peb 2255 falc-lh v1.3 functional description e1/t1/j1 data sheet 4 7 2000-07 3.3 functional blocks 3.3.1 microprocessor interface the communication between the cp u and the falc ? -lh is done via a set of directly accessible registers. the interface may be configured as intel or motorola type with a selectable data bus width of 8 or 16 bits. the cp u transfers data to/from the falc ? -lh (via 6 4 byte deep fifos per direction), sets the operating modes, controls function sequences, and gets status information by writing or reading control/status registers. all accesses can be done as byte or word accesses if enabled. if 16-bit bus width is selected, access to lower/upper part of the data bus is determined by address line a0 and signal bhe /ble as shown in table 6 and table 7 . in table 8 is shown how the ale (address latch enable) line is used to control the bus structure and interface type. the switching of ale allows the falc ? -lh to be directly connected to a multiplexed address/data bus. 3.3.1.1 mixed byte/word access to the fifos reading from or writing to the internal fifos (rfifo and x fifo) can be done using a 8 -bit (byte) or 16-bit (word) access depending on the selected bus interface mode. randomly mixed byte/word access to the fifos is allowed without any restrictions. if byte access is used, high byte or low byte can be used as well. any value written to high or low byte is placed in the fifo in sequential order.
peb 2255 falc-lh v1.3 functional description e1/t1/j1 data sheet 48 2000-07 table 6 data bus access (16-bit intel mode) table 7 data bus access (16-bit motorola mode) table 8 selectable bus and microprocessor interface configuration the assignment of registers with even/odd addresses to the data lines in case of 16-bit register access depends on the selected microprocessor interface mode: intel (address n + 1) (address n) motorola (address n) (address n + 1) n: even address bhe a0 register access falc ? -lh data pins used 0 0 fifo word access register word access (even addresses) d0...d15 0 1 register byte access (odd addresses) d 8 ...d15 1 0 register byte access (even addresses) d0...d7 1 1 no transfer performed none ble a0 register access falc ? -lh data pins used 0 0 fifo word access register word access (even addresses) d0...d15 0 1 register byte access (odd addresses) d0...d7 1 0 register byte access (even addresses) d 8 ...d15 1 1 no transfer performed none ale im microprocessor interface bus structure gnd/vdd 1 motorola demultiplexed gnd/vdd 0 intel demultiplexed switching 0 intel multiplexed data lines d15 d 8 d7 d0
peb 2255 falc-lh v1.3 functional description e1/t1/j1 data sheet 49 2000-07 3.3.1.2 fifo structure in transmit and receive direction of the signaling controller 6 4 -byte deep fifos are provided for the intermediate storage of data between the system internal highway and the cp u interface. the fifos are divided into two halves of 32-bytes. only one half is accessible to the cp u at any time. in case 16-bit data bus width is selected by fixing pin dbw to logical ?1? word access to the fifos is enabled. data output to bus lines d0-d15 as a function of the selected interfacemodeisshownin figure 7 and figure 8 . of course, byte access is also allowed. the effective length of the accessible part of rfifo can be changed from 32 bytes (reset value) down to 2 bytes by programming ccr1.rft1...0. figure 7 fifo word access (intel mode) 32 1 32 rfifo byte 4 byte 3 byte 2 byte 1 1 2 3 4 d15 d8 d7 d0 d0 d7 d8 d15 4 3 2 1 byte 1 byte 2 byte 3 byte 4 xfifo 32 1 32 itd01798
peb 2255 falc-lh v1.3 functional description e1/t1/j1 data sheet 50 2000-07 figure 8 fifo word access (motorola mode) 3.3.1.3 interrupt interface special events in the falc ? -lh are indicated by means of a single interrupt output with programmable characteristics (open drain, push-pull ; ipc register), which requests the cp u to read status information from the falc ? -lh, or to transfer data from/to falc ? - lh. since only one int request output is provided, the cause of an interrupt must be determined by the cp u by reading the falc?s interrupt status registers (gis, isr0...3, isr5) that means the interrupt at pin int and the interrupt status bits are reset by reading the interrupt status registers. register isr0...3,5 are from type ?clear on read?. the structure of the interrupt status registers is shown in figure 9 . 32 1 32 rfifo byte 4 byte 3 byte 2 byte 1 1 2 3 4 d15 d8 d7 d0 d0 d7 d8 d15 4 3 2 1 byte 1 byte 2 byte 3 byte 4 xfifo 32 1 32 itd01799
peb 2255 falc-lh v1.3 functional description e1/t1/j1 data sheet 51 2000-07 figure 9 interrupt status registers each interrupt indication of registers isr0?3,5 can be selectively masked by setting the corresponding bit in the corresponding mask registers imr0?3,5. if the interrupt status bits are masked they neither generate an interrupt at int nor are they visible in isr0 ? 3,5. gis, the non-maskable global interrupt status register, serves as pointer to pending interrupts. after the falc ? -lh has requested an interrupt by activating its int pin, the cp u should first read the global interrupt status register gis to identify the requesting interrupt source register. after reading the assigned interrupt status registers isr0...isr3 and isr5, the pointer in register gis is cleared or updated if another interrupt requires service. if all pending interrupts are acknowledged by reading (gis is reset), pin int goes inactive. u pdating of interrupt status registers isr0 ? 3,5 and gis is only prohibited during read access. masked interrupts visible in status registers the global interrupt status register (gis) indicates those interrupt status registers with active interrupt indications (gis.isr0...3,5). an additional mode can be selected via bit ipc.vis. in this mode, masked interrupt status bits neither generate an interrupt at pin int nor are they visible in gis, but are displayed in the respective interrupt status register(s) isr0...3,5 . this mode is useful when some interrupt status bits are to be polled in the individual interrupt status registers. its09740 isr0 isr1 isr3 isr2 gis isr3 imr3 imr0 isr0 isr1 imr1 imr2 isr2 isr5 imr5 isr5
peb 2255 falc-lh v1.3 functional description e1/t1/j1 data sheet 52 2000-07 note: in the visible mode, all active interrupt status bits, whether the corresponding actual interrupt is masked or not, are reset when the interrupt status register is read. thus, when polling of some interrupt status bits is desired, care must be taken that unmasked interrupts are not lost in the process. note: all unmasked interrupt statuses are treated as before. please note that whenever polling is used, all interrupt status registers concerned have to be polled individually (no ?hierarchical? polling possible), since gis only contains information on actually generated - i.e. unmasked-interrupts. 3.3.2 boundary scan interface identification register: 32 bit version: 4 h part number: 00 4 2h manufacturer:0 8 3h in falc ? -lh a test access port (tap) controller is implemented. the essential part of the tap is a finite state machine (16 states) controlling the different operational modes of the boundary scan. both, tap controller and boundary scan, meet the requirements given by the jtag standard: ieee 11 49 .1. figure 10 gives an overview.
peb 2255 falc-lh v1.3 functional description e1/t1/j1 data sheet 53 2000-07 figure 10 block diagram of test access port and boundary scan test handling is performed via the pins tc k (test clock), tms (test mode select), tdi (test data input) and tdo (test data output). test data at tdi are loaded with a 4 -mhz clock signal connected to tc k . ?1? or ?0? on tms causes a transition from one controller statetoanother ; constant ?1? on tms leads to normal operation of the chip. if no boundary scan testing is planned tms and tdi do not need to be connected since pull-up transistors ensure high input levels in this case. after switching on the device (power-on), a reset signal is generated internally, which forces the tap controller into test logic reset state. clock generation clock reset power on reset tap controller -finite state machine -instruction register (3 bits) -test signal generator tck tms tdi tdo clock test control data in control bus 6 id data out ss data out bs data in identification scan (32 bits) boundary scan (n bits) 1 2 n pins itb09842 enable data out test access port
peb 2255 falc-lh v1.3 functional description e1 data sheet 5 4 2000-07 4 functional description e1 4.1 receive path in e1 mode figure 11 receive clock system (e1) receive line interface for data input, three different data types are supported: ternary coded signals received at multifunction ports rl1 and rl2 from a -10 db (short haul, lim0.e q on = 0) or - 4 3 db (long haul, lim0.e q on = 1) ternary interface. the ternary interface is selected if lim1.drs is reset. digital dual rail signals received on ports rdip and rdin. the dual rail interface is selected if lim1.drs and fmr0.rc1 is set. u nipolar data on port roid received from a fiber optical interface. the optical interface is selected if lim1.drs is set and fmr0.rc1 is reset. alternatively the optical interface can be switched to pin 6 8 ( x mfb/ x oid) and pin 8 0 (roid) by setting bit loop.spn. equalizer clock & data recovery dpll line decoder alarm detector analog los detector rdata rcl k dco-r pd osc. s y nc x tal1 16.3 84 mhz cl k 16m cl k8 m cl kx fsc rl1/rdip/roid rl2/rdin/rcl k i f0057
peb 2255 falc-lh v1.3 functional description e1 data sheet 55 2000-07 long haul interface the falc ? -lh has an integrated short-haul and long-haul line interface, consisting of a receive equalization network and noise filtering. 4.1.1 receive equalization network (e1) the falc ? -lh automatically recovers the signals received on pins rl1/2 in a range of up to - 4 3 db. the maximum reachable length with a 22 awg twisted-pair cable is 1500 m. after reset the falc ? -lh is in ?short haul? mode, received signals are recovered up to -10 db of cable attenuation. switching in ?long haul? mode is done by setting of register lim0.e q on. the integrated receive equalization network recovers signals with up to - 4 3dbofcable attenuation. noise filters eliminate the higher frequency part of the received signals. the incoming data is peak detected and sliced at 55 % of the peak value to produce the digital data stream. the received data is then forwarded to the clock & data recovery unit. the current equalizer status is indicated by register res (receive equalizer status) in long haul mode. 4.1.2 receive line attenuation indication (e1) status register res reports the current receive line attenuation in a range of 0 to - 4 3db in 25 steps of approximately 1.7 db each. the least significant 5 bits of this register indicate the cable attenuation in db. these 5 bits are only valid in conjunction with the two most significant bits (res.ev1/0 = 01). 4.1.3 receive clock and data recovery (e1) the analog received signal on port rl1/2 is equalized and then peak-detected to produce a digital signal. the digital received signal on port rdip/n is directly forwarded to the dpll. the receive clock and data recovery extracts the route clock rcl k from the data stream received at the rl1/2, rdip/rdin or roid lines and converts the data stream into a single rail, unipolar bit stream. the clock and data recovery works with the clock frequency supplied by x tal1. normally the clock that is output via pin rcl k is the recovered clock from the signal provided on rl1/2 or rdip/n and has a duty cycle close to 50 % . the free run frequency is defined by x tal1 divided by 8 in periods with no signal. the intrinsic jitter generated in the absence of any input jitter is not more than 0.035 u i. in digital bipolar line interface mode the clock and data recovery accepts only hdb3 or ami coded signals with 50 % duty cycle. 4.1.4 receive line coding (e1) the hdb3 line code or the ami coding is provided for the data received from the ternary or the dual rail interface. in case of the optical interface a selection between the nr z code and the cmi code (1t2b) with hdb3 postprocessing is provided. if cmi code
peb 2255 falc-lh v1.3 functional description e1 data sheet 56 2000-07 (1t2b) is selected the receive route clock is recovered from the data stream. the 1t2b decoder does not correct any errors. in case of nr z coding data is latched with the falling edge of signal rcl k i. the hdb3 code is used along with double violation detection or extended code violation detection (selectable). in ami code all code violations is detected. the detected errors increment the code violation counter (16 bits length). when using the optical interface with nr z coding, the decoder is by-passed and no code violations are detected. the signal at the ternary interface is received at both ends of a transformer. the e1-operating modes 75 or 120 ? are selectable by switching resistors in parallel. this selection does not require changing transformers. figure 12 receiver configuration (e1) table 9 recommended receiver configuration values (e1) parameter characteristic impedance [ ? ] 120 75 r 2 ( 1 % ) [ ? ] 2 4 0150 t 2 : t 1 1: 1: its10967 line t 2 t 1 rl2 rl1 2 r r falc 2 2
peb 2255 falc-lh v1.3 functional description e1 data sheet 57 2000-07 4.1.5 loss of signal detection (e1) there are different definitions for detecting loss of signal (los) alarms in the it u -t g.775 and ets 300233. the falc ? -lh covers all these standards. the los indication is performed by generating an interrupt (if not masked) and activating a status bit. additionally a los status change interrupt is programmable via register ipc.sci. detection: an alarm is generated if the incoming data stream has no pulses (no transitions) for a certain number (n) of consecutive pulse periods. ?no pulse? in the digital receive interface means a logical zero on pins rdip/rdin/roid. a pulse with an amplitude less than q db below nominal is the criteria for ?no pulse? in the analog receive interface (lim1.drs = 0). in short haul mode (lim0.e q on = 0) the receive signal level q is programmable via three control bits lim1.ril2...0 in a range of about 1 4 00 to 200 mv differential voltage between pins rl1/2. in long haul mode (lim0.e q on = 1) the analog los criteria is defined by the equalizer status. the number n can be set via an 8 bit register pcd. the contents of the pcd register is multiplied by 16, which results in the number of pulse periods or better, the time which has to suspend until the alarm has to be detected. the range therefore results from 16 to 4 0 9 6pulse periods. ets300233 requires detection intervals of at least 1 ms. this time period results always in a lfa (loss of frame alignment) before a los is detected. recovery: in general the recovery procedure starts after detecting a logical ?one? (digital receive interface) or a pulse (analog receive interface) with an amplitude more than q db (defined by lim1.ril2...0, lim0.e q on = 0) of the nominal pulse. the value in the 8 bit register pcr defines the number of pulses (1 to 255) to clear the los alarm. additional recovery conditions may be programmed by register lim2. note: in long haul mode, los alarm is declared either if ? no pulses ? are detected for the period defined in pcd or the signal level drops below typically about -35 db of the nominal signal ( ? low signal level ? ). additionally, the incoming data stream is cleared, if this ? low signal level ? is detected in order to generate a fixed data stream before first bit errors occur. typically, this loss of signal threshold is about -35 db. for recovery this means, that at first the signal level has to increase and then the pulses are counted and compared to pcr to return from los indication. please also note, that this behavior is slightly different to falc-lh v1.1.
peb 2255 falc-lh v1.3 functional description e1 data sheet 5 8 2000-07 4.1.6 receive jitter attenuator (e1) the receive jitter attenuator is placed in the receive path. the jitter attenuator meets the requirements of it u -t i. 4 31,g.736-73 9 ,g. 8 23 and etsi tbr12/13. the internal dco-r generates a ?jitter free? output clock which is directly dependent on the phase difference of the incoming clock and the jitter attenuated clock.the receive jitter attenuator can be either synchronized with the extracted receive clock rcl k or to a2.0 48 -mhz clock provided on pin s y nc. the received data is written into the receive elastic buffer with rcl k and are read out with the dejittered clock cl k8 m/cl kx sourced by dco-r if it is connected to scl k r. optionally a 8 khz clock is provided on pin x cl k / fsc or fsc . the dco-r circuitry attenuates the incoming jittered clock starting at 2 hz jitter frequency with 20 db per decade fall off. wander with a jitter frequency below 2 hz is passed unattenuated. the intrinsic jitter in the absence of any input jitter is < 0.02 u i. for some applications it might be useful starting of jitter attenuation at lower frequencies. therefore the corner frequency is switchable by the factor of ten down to 0.2 hz (lim2.scf). jitter attenuation can be achieved either using an external tunable crystal on pins x tal1/ x tal2 or using the crystal-less jitter attenuation selected by lim2.dja1/2. in this case, a stable clock or regular crystal of 16.3 84 mhz has to be provided on pin x tal1 ( + /- 50 ppm). in crystal-less mode the system clock output on pin cl k 16m can be either the dejittered or the non-dejittered clock (lim3.csc). the dco-r circuitry is automatically centered to the nominal bit rate if the reference clock on pin s y nc/rcl k ismissedfortwo2.0 48 -mhz clock periods. in analog line interface mode the rcl k is always running. only in digital line interface mode with single rail data a gapped clock at rcl k i may occur. in this case, dco-r centers automatically. the receive jitter attenuator works in two different modes: slave mode in slave mode (lim0.mas = 0) the dco-r is synchronized with the recovered route clock. in case of los the dco-r switches to master mode automatically. master mode in master mode (lim0.mas = 1) the jitter attenuator is in free running mode if no clock on pin s y nc is supplied. if a 2.0 48 mhz clock at the s y nc input is applied the dco- r synchronizes to this input. the following table shows the clock modes with the corresponding synchronization sources.
peb 2255 falc-lh v1.3 functional description e1 data sheet 5 9 2000-07 the jitter attenuator meets the jitter transfer requirements of the recommendations i. 4 31 and g.735-73 9 (refer to figure 13 ). figure 13 jitter attenuation performance (e1) also the requirements of etsi tbr12/13 are satisfied. insuring adequate margin against tbr12/13 output jitter limit with 15 u i input at 20 hz the dco-r circuitry starts jitter attenuation at nearly 2 hz. table 10 system clocking (e1) mode internal los active sync input system clocks generated by dco-r master independent fixed to vss free running, dco-r centered master independent 2 mhz synchronized with s y nc input (external 2 mhz) slave no fixed to vss synchronized with line rcl k slave no 2 mhz synchronized with line rcl k slave yes fixed to vss free running, dco-r is centered slave yes 2 mhz synchronized with s y nc input (external 2.0 48 mhz) itd10312 1 -60 frequency attenuation 10 100 1000 10000 100000 hz itu g.736 template -50 -40 -30 -20 -10 0 10 db falc r
peb 2255 falc-lh v1.3 functional description e1 data sheet 60 2000-07 4.1.7 jitter tolerance (e1) the falc ? -lh receiver?s tolerance to input jitter complies to it u for cept application. figure 14 shows the curves of different input jitter specifications stated below as well as the falc ? -lh performance. figure 14 jitter tolerance (e1) 4.1.8 output jitter (e1) in the absence of any input jitter the falc ? -lh generates the output jitter, which is specified in the table 11 below. table 11 output jitter (e1) specification measurement filter bandwidth output jitter (ui peak to peak) lower cutoff upper cutoff it u -t i. 4 31 20 hz 100 khz < 0.02 700 hz 100 khz < 0.02 jitter amplitude jitter frequency 1 10 100 1000 10000 100000 hz u i 1 0.1 10 100 1000 p u b62 4 11 tr-nwt 000 499 cat ii ccitt g. 8 23 it u -t i. 4 31 falc ? f0025
peb 2255 falc-lh v1.3 functional description e1 data sheet 61 2000-07 4.1.9 transmit jitter attenuator (e1) the transmit jitter attenuator dco- x circuitry generates a ?jitter free? transmit clock and meets the following requirements: it u -t i. 4 31, g. 703, g. 736-73 9 ,g. 8 23 and etsi tbr12/13. the dco- x circuitry works internally with the same high frequency clock as the receive jitter attenuator it does. it synchronizes either to the working clock of the transmit backplane interface or the clock provided by pin s y nc2 or the receive clock rcl k (remote loop/loop-timed). the dco- x attenuates the incoming clock jitter starting at 6 hz with 20 db per decade fall off. with the jitter attenuated clock, which is directly dependent on the phase difference of the incoming clock and the jitter attenuated clock, data is read from the transmit elastic buffer or from the jatt buffer (remote loop with jatt). wander with a jitter frequency below 6 hz is passed transparently. the dco- x accepts gapped clocks which are used in atm or sdh/sonet applications. the jitter attenuated transmit clock is output by pin x cl k . in the loop-timed clock configuration (lim2.elt) the dco- x circuitry generates a transmit clock which is frequency synchronized with rcl k . in this configuration the transmit elastic buffer has to be enabled. dco- x can optionally be used with x tal1 clock reference (selected by lim1.tcd1 = 1). the dejittered transmit clock can be output on pin cl k 16m. in this case the clocks cl kx ,cl k8 and fsc are not synchronized with rcl k /s y nc.
peb 2255 falc-lh v1.3 functional description e1 data sheet 62 2000-07 figure 15 transmit clock system (e1) note: dr = dual rail interface dco-r digital controlled oscillator receive dco-x digital controlled oscillator transmit 4.1.10 framer/synchronizer the following functions are performed: synchronization on pulse frame and multiframe error indication when synchronization is lost. in this case, ais is automatically sent to the system side and remote alarm to the remote end if en/disabled. initiating and controlling of resynchronization after reaching the asynchronous state. this can be done automatically by the falc ? -lh, or user controlled via the microprocessor interface. detection of remote alarm indication from the incoming data stream. separation of service bits and data link bits. this information is stored in status registers. generation of various maskable interrupt statuses of the receiver functions. d a pulse shaper framer elastic store x di dco- x pd osc. lim1.tcd 1 scl kx s y nc2 rcl k x cl k x tal1 16.3 84 mhz x tal3 16.3 84 mhz 8 mhz 2 mhz f0047
peb 2255 falc-lh v1.3 functional description e1 data sheet 63 2000-07 generation of control signals to synchronize the crc checker and the receive elastic buffer. if programmed and applicable to the selected multiframe format, crc checking of the incoming data stream is done by generating check bits for a crc submultiframe according to the crc 4 procedure (refer to it u -t g70 4 ). these bits are compared with those check bits that are received during the next crc submultiframe. if there is at least one mismatch, the crc error counter (16 bit) is incremented. 4.1.11 receive elastic buffer (e1) the received bit stream is stored in the receive elastic buffer. the memory is organized as a two-frame elastic buffer with a maximum size of 6 4 8 bit. the size of the elastic buffer can be configured independently for the receive and transmit direction. programming of the receive buffer size is done by sic1.rbs1/0 : rbs1/0 = 00 : two frame buffer or 512 bits maximum of wander amplitude (peak-to-peak): 1 9 0 u i(1 u i = 488 ns ) average delay after performing a slip: about 1 frame rbs1/0 = 01 : one frame buffer or 256 bits max. wander amplitude: 94 u i average delay after performing a slip: 12 8 bits, (s y pr = output) rbs1/0 = 10 : short buffer or 9 2bits: max. wander amplitude: 1 8 s average delay after performing a slip: 4 6bits,(s y pr = output) rbs1/0 = 11 : bypass of the receive elastic buffer, (s y pr = output) the functions are: clock adaption between system clock (scl k r) and internally generated route clock (rcl k ). compensation of input wander and jitter. frame alignment between system frame and receive route frame reporting and controlling of slips controlled by special signals generated by the receiver, the unipolar bit stream is converted into bit-parallel data which is circularly written to the elastic buffer using internally generated receive route clock (rcl k ). reading of stored data is controlled by the system clock sourced by scl k randthe synchronous pulse (s y pr ) in conjunction with the programmed offset values for the receive time slot/clock slot counters. after conversion into a serial data stream, the data
peb 2255 falc-lh v1.3 functional description e1 data sheet 6 4 2000-07 is given out via port rdo. if the receive buffer is bypassed, data is clocked off with rcl k instead of scl k r. in one frame or short buffer mode the delay through the receive buffer is reduced to an average delay of 12 8 or 4 6 bits. slips are performed in all buffer modes except the bypass mode. after a slip is detected the read pointer is adjusted to one half of the current buffer size. the following table gives an overview of the receive buffer operating mode. note: combinations of sic1.rbs1...0 and loop.sfm other than described are not allowed. the use of loop.sfm = 1 is not recommended, but possible for falc ? 54 compatibility. . table 12 receive buffer operating modes (e1) sic1.rbs1...0 buffer size ts offset programing (rc1...0) slip performance 11 loop.sfm = 0 bypass 1) 1) in bypass mode the clock provided on pin scl k r is ignored. clocking is done with rcl k . rfm (s y pr = output) must be selected ; value of rc1...0 determines the position of rfm no slips 10 loop.sfm = 0 short buffer rfm (s y pr = output) must be selected ; value of rc1...0 determines the position of rfm yes 01 loop.sfm = 0 1frame rfm(s y pr = output) must be selected ; value of rc1...0 determines the position of rfm yes 00 loop.sfm = 1 1frame s y pr is input and determines the frame position together with rc1...0 offset. slip conditions are detected and reported, but no slip is performed. slipshavetobeinitiated by software (reprogramming of rc1...0). 00 loop.sfm = 0 2frames s y pr is input and determines the frame position together with rc1...0 offset. yes slips are performed on the frame boundary
peb 2255 falc-lh v1.3 functional description e1 data sheet 65 2000-07 in single frame mode ( sic1. rbs), values of receive time slot offset (rc1/0) have to be specified great enough to prevent too great approach of frame begin (line side) and frame begin (system side). figure 16 gives an idea of operation of the receive elastic buffer: a slip condition is detected when the write pointer (w) and the read pointer (r) of the memory are nearly coincident, i.e. the read pointer is within the slip limits (s + ,s?).ifa slip condition is detected, a negative slip (one frame or one half of the current buffer size is skipped) or a positive slip (one frame or one half of the current buffer size is read out twice) is performed at the system interface, depending on the difference between rcl k and the current working clock of the receive backplane interface. i.e. on the position of pointer r and w within the memory. a positive/negative slip is indicated in the interrupt status bits isr3.rsp and isr3.rsn. figure 16 the receive elastic buffer as circularly organized memory limits for slip detection (mode dependent) read pointer (system clock controlled) write pointer (route clock controlled) r ? s+, s- r : : w: frame 2 time slots s- r frame 1 time slots moment of slip detection itd10952 w s+ slip
peb 2255 falc-lh v1.3 functional description e1 data sheet 66 2000-07 4.1.12 receive signaling controller (e1) the signaling controller can be programmed to operate in various signaling modes. the falc ? -lh performs the following signaling and data link methods: 4.1.12.1 hdlc or lapd access in case of common channel signaling the signaling procedure hdlc/sdlc or lapd according to q . 9 21 is supported. the signaling controller of the falc ? -lh performs the flag detection, crc checking, address comparison and zero bit-removing. the received data flow and the address recognition features can be performed in very flexible way, to satisfy almost any practical requirements. depending on the selected address mode, the falc ? -lh performs a 1 or 2 byte address recognition. if a 2-byte address field is selected, the high address byte is compared with the fixed value feh or fch (group address) as well as with two individually programmable values in rah1 and rah2 registers. according to the isdn lapd protocol, bit 1 of the high byte address is interpreted as command/response bit (c/r) and is excluded from the address comparison. buffering of receive data is done in a 6 4 byte deep rfifo. in signaling controller transparent mode, fully transparent data reception without hdlc framing is performed, i.e. without flag recognition, crc checking or bit-stuffing. this allows user specific protocol variations. the falc ? -lh offers the flexibility to extract data during certain time slots. any combination of time slots may be programmed independently for the receive and transmit direction. 4.1.12.2 s a bit access (e1) the falc ? -lh supports the s a bit signaling of time slot 0 of every other frame as follows: the access via register rsw the access via registers rsa 4 - 8 , capable of storing the information for a complete multiframe the access via the 6 4 byte deep receive fifo of the signaling controller. this s a bit access gives the opportunity to receive a transparent bit stream as well as hdlc frames where the signaling controller automatically processes the hdlc protocol. any combination of s a bits which should be extracted and stored in the rfifo may be selected by x c0.sa 8 e-sa 4 e. the access to the rfifo is supported by isr0.rme/rpf. 4.1.12.3 channel associated signaling cas (e1, serial mode) the signaling information is carried in time slot 16 (ts16). the signaling controller samples the bit stream on the receive system side (selected by setting loop.spn = 1, lim3.es y= 1).
peb 2255 falc-lh v1.3 functional description e1 data sheet 67 2000-07 the complete cas multiframe can be transmitted on pin rsig. the signaling data is clocked with the working clock of the receive highway in conjunction with the receive synchronization pulse (s y pr /rfm). data on rsig is transmitted in the last 4 bits per time slot and are aligned to the data on rdo. the first 4 bits per time slot can be optionally fixed high or low, except for time slot 0 and 16. in time slot 0 the fas/nfas word is transmitted, in time slot 16 the cas multiframe pattern. data on rsig is valid only if the freeze signaling status is inactive. in case of freeze status, old data are repeated. with fmr1.sais = 1 an all-ones data stream may be transmitted on rdo and rsig. the signaling procedure is done as it is described in it u -t g.70 4 and g.732. the main functions are: synchronization to a cas multiframe detection of ais and remote alarm in cas multiframes separation of cas service bits u pdating of the receive signaling information is controlled by the freeze signaling status. the freeze signaling status is output on pin rfsp /free z s and is generated, if: bit frs1.tsl16lfa = 1or frs0.los = 1or a receive slip occurred the receive signaling buffer is updated if the alarm remains inactive for at least one complete cas multiframe. setting of bit sic2.ffs forces the freeze status active. the current freeze status could be read in register sis.sfs. optionally automatic freeze signaling may be disabled by setting bit sic3.daf. the cas controller acts on the pcm highway side of the receive buffer. therefore slips disturb cas data.
peb 2255 falc-lh v1.3 functional description e1 data sheet 6 8 2000-07 figure 17 2.048 mhz receive signaling highway (e1) 4.1.12.4 channel associated signaling cas (e1, p access mode) the signaling information is carried in time slot 16 (ts16). receive data is stored in registers rs1-16 aligned to the cas multiframe boundary. the signaling controller samples the bit stream on the receive line side. the signaling procedure is done as it is described in it u -t g.70 4 and g.732. the main functions are: synchronization to a cas multiframe detection of ais and remote alarm in cas multiframes separation of cas service bits storing of received data in registers rs1...16 with last look capability u pdating of the receive signaling information is controlled by the freeze signaling status. if signaling information is frozen updating of the registers rs1...16 is disabled. the freeze signaling status is output on pin rfsp /free z s and is generated, if: bit frs1.tsl16lfa = 1 the receive signaling buffer is updated if the alarm remains inactive for at least one complete cas multiframe. to relieve the p load from always reading the complete rs1-16 buffer every 2 ms the falc ? -lh notifies the p via interrupt isr0.casc only when signaling changes from one multiframe to the next. the cas controller acts on the pcm highway side of the receive buffer. therefore slips disturb cas data. itt10517 0123456701234567 01234567 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ d c b a abcd d c b a fas / nfas ts0 ts1 ts31 ts31 125 s t sypr sclkr rdo rsig t = time-slot offset (register rc1/0) = frame alignment signal fas = ts0 not containing the fas word nfas = signaling bits for time-slot 1-30 of cas multiframe abcd ~ ~
peb 2255 falc-lh v1.3 functional description e1 data sheet 6 9 2000-07 4.2 system interface in e1 mode the falc ? -lh offers a flexible feature for system designers where for transmit and receive direction different system clocks and system pulses are necessary. the interface to the receive system highway is realized by two data buses, one for the data rdo and one for the signaling data rsig. the receive highway is clocked via pin scl k r/rcl k , while the interface to the transmit system highway is independently clocked via pin scl kx . selectable system clock and data rates and their valid combinations are shown in the table below. generally the data or marker on the system interface are clocked off or latched on the falling edge of the scl k r/ x clock. 8 .1 9 2-mhz clocking rate allows transmitting of time slots in different channel phases. the active channel phase is selected by rc0.sics, during the inactive channel phase the output signal is tristated. the signals on pin s y pr in conjunction with the assigned timeslot offset in register rc0 and rc1 define the beginning of a frame on the receive system highway. the signal on pin s y p x in conjunction with the assigned timeslot offset in register x c0 and x c1 define the beginning of a frame on the transmit system highway. adjusting the frame begin (time slot 0, bit 0) relative to s y pr/ x canbeprogrammedin clock steps in the range of 0...125 sec. a receive frame marker rfm can be activated during any bit position of the entire frame. programming is done with registers rc1/0. the pin function rfm is selected by sic2.srfs0. the receive frame marker is active high for one 2.0 48 mhz cycle (2.0 48 mbit/s pcm highway interface mode) or two 8 .1 9 2 mhz cycles ( 4 .0 9 6mbit/spcm highway interface mode) and is clocked off with the falling edge of the clock which is in/ output on port scl k r. table 13 system clock and data rates (e1) system data rate clock rate 2.048 mhz clock rate 8.192 mhz 2.0 48 mbit/s x 1) 1) x = valid ; -- = invalid x 4 .0 9 6mbit/s -- x
peb 2255 falc-lh v1.3 functional description e1 data sheet 70 2000-07 figure 18 system interface (e1) receive elastic buffer receive jitter attenuator receive backplane transmit backplane receive data transmit data receive clock transmit clock s y nc2 rcl k plb b y p b y p transmit jitter attenuator scl k r scl kx rsigm s y pr rfm rmfb dlr/rsig rdo x sig x sigm x mfb dl x x di x mfs s y p x system clocks transmit elastic buffer s y nc b y p f0050
peb 2255 falc-lh v1.3 functional description e1 data sheet 71 2000-07 figure 19 receive system interface clocking (e1) itd10951 ~ ~ ~ ~ frame 1 frame 2 frame 3 frame 15 frame 16 frame 1 frame 2 frame 15 ~ ~ ~ ~~ ~ ~ ~ ~ ~ bit 255 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 2 bit 1 bit 0 bit 255 t multi frame 1 multi frame 2 4 mbit interface 2 mbit interface programmable via rc0/1 rdo rmfb sypr sypr sclkr 8.192 mhz 2.048 mhz sclkr 2 mbit/s data rate rdo/rsig ts0 rdo/rsig (sclkr = 8.192 mhz) 4 mbit/s data rate dlr sa-bit marker xc0 . sa8e-sa4e receive frame marker rfm rc0/1 rsigm time-slot marker rtr1...4 4 mbit/s data rate (sclkr = 8.192 mhz) rdo/rsig trigger edge edge sample marks any sa bit bit position marks any marks any time-slot 4 mbit interface 2 mbit interface bit 3 bit 4 bit 5 bit 6 bit 7 1) only falling trigger edge shown, depending on bit sic3.resr 1)
peb 2255 falc-lh v1.3 functional description e1 data sheet 72 2000-07 4.2.1 time slot assigner (e1) the falc ? -lh offers the flexibility to c onnect data during certain time slots, as defined by registers rtr1- 4 and ttr1- 4 , to the rfifo and x fifo, respectively. any combinations of time slots can be programmed for the receive and transmit directions. if ccr1.eits = 1 the selected time slots (rtr1- 4 ) are stored in the rfifo of the signaling controller and the x fifo contents are inserted into the transmit path as controlled by registers ttr1- 4 . table 14 time slot assigner (e1) receive time slot register transmit time slot register time slots receive time slot register transmit time slot register time slots rtr 1.7 ttr 1.7 0 rtr 3.7 ttr 3.7 16 rtr 1.6 ttr 1.6 1 rtr 3.6 ttr 3.6 17 rtr 1.5 ttr 1.5 2 rtr 3.5 ttr 3.5 1 8 rtr 1. 4 ttr 1. 4 3rtr3. 4 ttr 3. 4 1 9 rtr 1.3 ttr 1.3 4 rtr 3.3 ttr 3.3 20 rtr 1.2 ttr 1.2 5 rtr 3.2 ttr 3.2 21 rtr 1.1 ttr 1.1 6 rtr 3.1 ttr 3.1 22 rtr 1.0 ttr 1.0 7 rtr 3.0 ttr 3.0 23 rtr 2.7 ttr 2.7 8 rtr 4 .7 ttr 4 .7 2 4 rtr 2.6 ttr 2.6 9 rtr 4 .6 ttr 4 .6 25 rtr 2.5 ttr 2.5 10 rtr 4 .5 ttr 4 .5 26 rtr 2. 4 ttr 2. 4 11 rtr 4 . 4 ttr 4 . 4 27 rtr 2.3 ttr 2.3 12 rtr 4 .3 ttr 4 .3 2 8 rtr 2.2 ttr 2.2 13 rtr 4 .2 ttr 4 .2 2 9 rtr 2.1 ttr 2.1 1 4 rtr 4 .1 ttr 4 .1 30 rtr 2.0 ttr 2.0 15 rtr 4 .0 ttr 4 .0 31
peb 2255 falc-lh v1.3 functional description e1 data sheet 73 2000-07 4.3 transmit path in e1 mode compared to the receive path the inverse functions are performed for the transmit direction. the interface to the transmit system highway is realized by two data buses, one for the data x di and one for the signaling data x sig. the time slot assignment is equivalent to the receive direction. latching of data is controlled by the system clock (scl kx ) and the synchronous pulse (s y p x / x mfs) in conjunction with the programmed offset values for the transmit time slot/clock slot counters x c1/0. refer also to table 13 on page 69 . the received bit stream on ports x di and x sig can be multiplexed internally on a time slot basis, if enabled by sic3.ttrf = 1, if not serial cas mode is selected (see chapter 4.1.12.3 on page 66 ).thedatareceivedonport x sig can be sampled if the transmit signaling marker x sigm is active high. data on port x di is sampled if x sigm is low for the respective time slot. programming the x sigm marker is done with registers ttr1- 4 .
peb 2255 falc-lh v1.3 functional description e1 data sheet 7 4 2000-07 figure 20 transmit system interface clocking: 2.048 mhz (e1) frame0 frame1 frame2 frame15 frame0 frame1 frame2 multi frame 1 multi frame 2 x di x mfb x mfs s y p x trigger edge bit 0 sample edge scl kx x di/ x sig bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 dl x sa-bit marker x c0.sa 8 e-sa 4 e bit 4 marked 1) delay t is programmable by x c0/1 ; s y p x t 1) x sigm ts0 f0031
peb 2255 falc-lh v1.3 functional description e1 data sheet 75 2000-07 figure 21 transmit system interface clocking: 8.192 mhz/4.096 mbit/s (e1) frame0 frame1 frame2 frame15 frame0 frame1 frame2 multi frame 1 multi frame 2 x di x mfb x mfs s y p x trigger edge bit 0 sample edge scl kx x di/ x sig rc0.sics = 0 dl x sa-bit marker x c0.sa 8 e-sa 4 e rc0.sics = 0 bit 4 marked 1) delay t is programmable by x c0/1 ; s y p x t 1) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 bit 4 marked dl x sa-bit marker x c0.sa 8 e-sa 4 e rc0.sics = 0 x di/ x sig rc0.sics = 1 x sigm time-slot marker ttr1... 4 rc0.sics = 0 f0029
peb 2255 falc-lh v1.3 functional description e1 data sheet 76 2000-07 4.3.1 transmit signaling controller (e1) similar to the receive signaling controller the same signaling methods and the same time slot assignment is provided. the falc ? -lh performs the following signaling and data link methods: 4.3.1.1 hdlc or lapd access the transmit signaling controller of the falc ? -lh performs the flag generation, crc generation, zero bit-stuffing and programmable idle code generation. buffering of transmit data is done in the 6 4 byte deep x fifo. the signaling information is internally multiplexed with the data applied to port x di or x sig. in signaling controller transparent mode, fully transparent data transmission without hdlc framing is performed. optionally the falc ? -lh supports the continuous transmission of the x fifo contents. the falc ? -lh offers the flexibility to insert data during certain time slots. any combinations of time slots may be programmed separately for the receive and transmit directions. 4.3.1.2 s a bit access (e1) the falc ? -lh supports the s a bit signaling of time slot 0 of every second frame as follows: - the access via register x sw - the access via registers x sa 4 e... x sa 8 e, capable of storing the information for a complete multiframe - the access via the 6 4 byte deep x fifo of the signaling controller. this s a bit access gives the opportunity to send a transparent bit stream as well as hdlc frames where the signaling controller automatically processes the hdlc protocol. any combination of s a bits which shall be inserted into the outgoing data stream may be selected by x c0.sa 4 e...sa 8 e. 4.3.1.3 channel associated signaling cas (e1, serial access mode) in external signaling mode the signaling data is received on port x sig. the signaling data is sampled with the working clock of the transmit system interface (scl kx )in conjunction with the transmit synchronization pulse (s y p x ). data on x sig is latched in the bit positions 5... 8 per time slot, bits 1... 4 are ignored. time slot 0 and 16 are sampled completely (bit 1... 8 ). the received cas multiframe is inserted frame aligned into the data stream on x di. data sourced by the internal signaling controller overwrites the external signaling data. cas data is read from x sig during the last frame of a multiframe, if crc 4 /multiframe mode is selected. the cas-multiframe is aligned to the crc 4 -multiframe. other frames are ignored.
peb 2255 falc-lh v1.3 functional description e1 data sheet 77 2000-07 if the falc ? -lh is optioned for no signaling, the data stream from the system interface passes the falc ? -lh undisturbedly. figure 22 2.048 mhz transmit signaling highway (e1) 4.3.1.4 channel associated signaling cas (e1, p access mode) transmit data stored in registers x s1-16 is transmitted in time slot 16 aligned to the multiframe boundary. the signaling controller inserts the bit stream either on the transmit line side or if external signaling is enabled on the transmit system side via pin function x sig. data sourced by the internal signaling controller overwrites the external signaling data. if the falc ? -lh is optioned for no signaling, the data stream from the system interface passes the falc ? -lh undisturbedly. 4.3.2 transmit elastic buffer (e1) the received bit stream from pin x di is optionally stored in the transmit elastic buffer. the memory is organized as the receive elastic buffer. the functions are also equal to the receive side. programming of the transmit buffer size is done by sic1. x bs1/0 : x bs1/0 = 00 : bypass of the transmit elastic buffer x bs1/0 = 01 : one frame buffer or 256 bits max. wander amplitude (peak-to-peak): 94 u i(1 u i =488 ns ) average delay after performing a slip: 12 8 bits x bs1/0 = 10 : two frame buffer or 512 bits maximum of wander amplitude: 1 9 0 u i average delay after performing a slip: 1 frame or 256 bits itt10518 0123456701234567 01234567 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ d c b a abcd d c b a fas / nfas ts0 ts1 ts31 ts31 125 s t sypx sclkx xdi xsig t = time-slot offset (register xc1/0) = frame alignment signal fas = ts0 not containing the fas word nfas = signaling bits for time-slot 1-30 of cas multiframe abcd ~ ~
peb 2255 falc-lh v1.3 functional description e1 data sheet 7 8 2000-07 x bs1/0 = 11 : short buffer or 9 2bits: max. wander amplitude: 1 8 s average delay after performing a slip: 4 6bits the functions of the transmit buffer are: clock adaption between system clock (scl kx ) and internally generated transmit clock ( x cl k ). compensation of input wander and jitter. frame alignment between system frame and transmit line frame reporting and controlling of slips writing of received data from x di is controlled by scl kx and s y p x / x mfs in conjunction with the programmed offset values for the transmit time slot/clock slot counters. reading of stored data is controlled by the clock generated by dco- x circuitry and the transmit framer. with the dejittered clock data is read from the transmit elastic buffer and are forwarded to the transmitter. reporting and controlling of slips is done according to the receive direction. positive/negative slips are reported in interrupt status bits isr5. x sp and isr5. x sn. if the transmit buffer is bypassed data is directly transferred to the transmitter. the following table gives an overview of the transmit buffer operating modes. 4.3.3 transmitter (e1) the serial bit stream is then processed by the transmitter which has the following functions: frame/multiframe synthesis of one of the two selectable framing formats insertion of service and data link information ais generation (alarm indication signal) remote alarm generation crc generation and insertion of crc bits crc bits inversion in case of a previously received crc error idle code generation per ds0 table 15 transmit buffer operating modes (e1) sic1. x bs1...0 buffer size ts offset programming slip performance 00 bypass enabled no 11 short buffer enabled yes 01 1 frame enabled yes 10 2 frames enabled yes if x sw. x tm = 1, slip is performed on the frame boundary
peb 2255 falc-lh v1.3 functional description e1 data sheet 7 9 2000-07 auxiliary pattern generation the frame/multiframe boundaries of the transmitter may be externally synchronized by using the s y p x / x mfs pin. any change of the transmit time slot assignment subsequently produces a change of the framing bit positions on the line side. this feature is required if signaling- and service- bits are routed through the switching network and are inserted in transmit direction via the system interface. in loop-timed configuration (lim2.elt) disconnecting the control of the transmit system highway from the transmitter is done by setting x sw. x tm. the transmitter is now in a free running mode without any possibility to update the multiframe position in case of changing the transmit time slot assignment. the framing bits are generated independent of the transmit system interface. for proper operation the transmit elastic buffer size should be programmed to 2 frames. the contents of selectable time slots can be overwritten by the pattern defined via register idle. the selection of ?idle channels? is done by programming the four-byte registers icb1 ? icb 4 . 4.3.4 transmit line interface (e1) the analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar) return to zero signals of the appropriate programmable shape. the unipolar data is provided by the digital transmitter. figure 23 transmitter configuration (e1) table 16 example transmitter configuration values (e1) parameter 1) 1) includes all parasitics characteristic impedance [ ? ] 120 75 r 1 ( 1 % ) [ ? ] 1 8 1 8 t2 : t1 1 : 1 : its10968 line t 1 t 2 xl2 xl1 r 1 1 r falc r 2 2
peb 2255 falc-lh v1.3 functional description e1 data sheet 8 0 2000-07 similar to the receive line interface three different data types are supported: ternary signal single rail data is converted into a ternary signal which is output on pins x l1 and x l2. the hdb3 and ami line code is employed. selected by fmr0. x c1/0 and lim1.drs = 0. dual rail data pcm( + ), pcm(?) at multifunction ports x dop/ x don with 50 % or 100 % duty cycle and with programmable polarity. line coding is done in the same way as in the ternary interface. selected by fmr0. x c1/0 and lim1.drs = 1. u nipolar data on port x oid is transmitted either in nr z (non return to z ero) with 100 % duty cycle or in cmi (code mark inversion or known as 1t2b) code with or without (fmr3.cmi) preprocessed hdb3 coding to a fibre optical interface. clocking off data is done with the rising edge of the transmit clock x cl k (20 48 khz) and with a programmable polarity. selection is done by fmr0. x c1 = 0 and lim1.drs = 1. 4.3.5 programmable pulse shaper (e1) the analog transmitter includes a programmable pulse shaper to satisfy the requirements of it u -t i. 4 31. the amplitude and shape of the transmit pulses are completely programmable via registers x pm0...2 from the microprocessor interface. the transmitter requires an external step up transformer to drive the line. 4.3.6 transmit line monitor (e1) the transmit line monitor compares the transmit line pulses on x l1 and x l2 with the transmit input signals received on pins x l1m and x l2m. the monitor detects faults on the primary side of the transformer and protects the device from damage by setting the transmit lines into high impedance state automatically. faults on the secondary side can not be detected. to detect shorts, the configuration shown in figure 24 must be provided and the default (reset) value of registers x pm0...2 must be selected. otherwise a short detection can not be guaranteed. two conditions are detected by the monitor: ?transmit line ones density? (more than 31 consecutive zeroes) and ?transmit line shorted?. in both cases a transmit line monitor status change interrupt is provided.
peb 2255 falc-lh v1.3 functional description e1 data sheet 8 1 2000-07 figure 24 transmit line monitor configuration (e1) its09746 pulse shaper monitor line tri xpm2.daxlt/xlt xdata xl1 xl2 xl2m xl1m r falc -lh
peb 2255 falc-lh v1.3 functional description e1 data sheet 8 2 2000-07 4.4 framer operating modes (e1) 4.4.1 general bit: fmr1.pmod = 0 pcm line bit rate : 2.0 48 mbit/s single frame length : 256 bit, no. 1 ? 256 framing frequency : 8 khz hdlc controller : nx6 4 kbit/s, n = 1...32 or nx 4 kbit/s, n = 1...5 organization : 32 time slots, no. 0 ? 31 with 8 bits each, no. 1 ? 8 the operating mode of the falc ? -lh is selected by programming the carrier data rate and characteristics, line code, multiframe structure, and signaling scheme. the falc ? -lh implements all of the standard framing structures for e1 or pcm 30 (cept, 2.0 48 mbit/s) carriers. the internal hdlc- or cas controller supports all signaling procedures including signaling frame synchronization/synthesis and signaling alarm detection in all framing formats. the time slot assignment from the pcm line to the system highway and vice versa. is performed without any changes of numbering (ts0 ? ts0, ? , ts31 ? ts31). summary of e1- framing modes doubleframe format according to it u -t g. 70 4 multiframe format according to it u -t g. 70 4 crc 4 processing according to it u -t g. 706 multiframe format with crc 4 to non crc 4 interworking according to it u -t g. 706 multiframe format with modified crc 4 to non crc 4 interworking multiframe format with crc 4 performance monitoring after reset, the falc ? -lh is switched into doubleframe format automatically. switching between the framing formats is done via bit fmr2.rfs1/0 and fmr3.e x tiw for the receiver and fmr1. x fs for the transmitter.
peb 2255 falc-lh v1.3 functional description e1 data sheet 8 3 2000-07 4.4.2 doubleframe format (e1) the framing structure is defined by the contents of time slot 0 (refer to table 17 ).) note: 1. s i bits: reserved for international use. if not used, these bits should be fixed to ? 1 ? . access to received information via bits rsw.rsi and rsp.rsif. transmission is enabled via bits xsw.xsis and xsp.xsif. 2. fixed to ? 1 ? . used for synchronization. 3. remote alarm indication: in undisturbed operation ? 0 ? ; in alarm condition ? 1 ? . 4. s a bits: reserved for national use. if not used, they should be fixed at ? 1 ? .accessto received information via bits rsw.ry0 ? ry4. transmission is enabled via bits xsw.xy0 ? xy4. hdlc-signaling in bits sa4- sa8 is selectable. (*) note: (*) as a special extension for double frame format, the s a -bit registers rsa4-8 ? xsa4-8 may be used optionally. 4.4.2.1 transmit transparent modes in transmit direction, contents of time slot 0 frame alignment signal of the outgoing pcm frame are normally generated by the falc ? -lh. however, transparency for the complete time slot 0 can be achieved by selecting the transparent mode x sp.tt0. with the transparent service word mask register tswm the s i -bits, a-bit and the sa 4 - 8 bits can be selectively switched through transparently. x sw. x tm = 0 must be selected. table 17 allocation of bits 1 to 8 of time slot 0 (e1) bit number alternate frames 12 345678 frame containing the frame alignment signal s i 0 011011 note 1 frame alignment signal frame not containing the frame alignment signal or service word s i 1as a 4 s a5 s a6 s a7 s a 8 note 1 note 2 note 3 note 4
peb 2255 falc-lh v1.3 functional description e1 data sheet 84 2000-07 figure 25 data flow in transparent mode 4.4.2.2 synchronization procedure synchronization status is reported via bit frs0.lfa. framing errors are counted by the framing error counter (fec). asynchronous state is reached after detecting 3 or 4 consecutive incorrect fas words or 3 or 4 consecutive incorrect service words (bit 2 = 0 in time slot 0 of every other frame not containing the frame alignment word), the selection is done via bit rc1.as y4 . additionally, the service word condition can be disabled. when the framer lost its synchronization an interrupt status bit isr2.lfa is generated. in asynchronous state, counting of framing errors and detection of remote alarm is stopped. ais is automatically sent to the backplane interface (can be disabled via bit fmr2.dais). further on the updating of the registers rsa6s and rs1-16 is halted (remote alarm indication, s a /s i -bit access). table 18 transmit transparent mode (doubleframe e1) transmit transparent source for enabled by framing a bit s a bits s i bits ? x sp.tt0 tswm.tsif tswm.tsis tswm.tra tswm.tsa 4 - 8 (int. generated) via pin x di 1) (int. generated) (int. generated) (int. generated) (int. generated) 1) pin x di or x sig or x fifo-buffer (signaling controller) x sw. x ra 2) via pin x di x sw. x ra x sw. x ra via pin x di x sw. x ra 2) additionally, automatic transmission of the a-bit is selectable x sw. xy 0? 4 3) via pin x di x sw. xy 0? 4 x sw. xy 0? 4 x sw. xy 0? 4 via pin x di 3) as a special extension for double frame format, the sa-bit register may be used optionally. x sw. x sis, x sp. x sif via pin x di via pin x di via pin x di x sw. x sis, x sp. x sif x sw. x sis, x sp. x sif x sw x sa 8 ... 4 x di x l1/2 tswm bits fmr1.ensa tt0 framing service word x sig sic3.ttrf ttr1... 4 f0059
peb 2255 falc-lh v1.3 functional description e1 data sheet 8 5 2000-07 the resynchronization procedure starts automatically after reaching the asynchronous state. additionally, it may be invoked user controlled via bit: fmr0.frs (force resynchronization: the fas word detection is interrupted until the framer is in the asynchronous state. after that, resynchronization starts automatically). synchronous state is established after detecting: a correct fas word in frame n, the presence of the correct service word (bit 2 = 1) in frame n + 1, a correct fas word in frame n + 2. if the service word in frame n + 1 or the fas word in frame n + 2 or both are not found searching for the next fas word starts in frame n + 2 just after the previous frame alignment signal. reaching the synchronous state causes a frame alignment recovery interrupt status isr2.far if enabled. u ndisturbed operation starts with the beginning of the next doubleframe. 4.4.2.3 a-bit access if the falc ? -lh detects a remote alarm indication in the received data stream the interrupt status bit isr2.ra is set. with setting of bit x sw. x ra a remote alarm (rai) is send to the far end. by setting fmr2.a x ra the falc ? -lh automatically transmit the remote alarm bit = 1in the outgoing data stream if the receiver detects a loss of frame alignment frs0.lfa = 1. if the receiver is in synchronous state frs0.lfa = 0 the remote alarm bit is reset. note: the a-bit may be processed via the system interface. setting bit tswm.tra enables transparency for the a bit in transmit direction (refer to table table 18 ). 4.4.2.4 s a - bit access as an extension for access to the s a -bits via registers rsa 4 - 8 / x sa 4 - 8 an option is implemented to allow the usage of internal s a -bit registers rsa 4 - 8 / x sa 4 - 8 in doubleframe format. this function is enabled by setting fmr1.ensa = 1 for the transmitter and fmr1.rfs1/ 0 = 01 for the receiver. the falc ? -lh works then internally with a 16-frame structure but no crc multiframe alignment/generation is performed.
peb 2255 falc-lh v1.3 functional description e1 data sheet 8 6 2000-07 4.4.3 crc-multiframe (e1) the multiframe structure shown in table 19 table is enabled by setting bit: fmr2.rfs1/0 for the receiver and fmr1. x fs for the transmitter. multiframe : 2 submultiframes = 2 8 frames frame alignment : refer to section doubleframe format multiframe alignment : bit 1 of frames 1, 3, 5, 7, 9 , 11 with the pattern ?001011? crcbits : bit1offrames0,2, 4 ,6, 8 , 10, 12, 1 4 crc block size : 20 48 bit (length of a submultiframe) crc procedure : crc 4 , according to it u -t g.70 4 , g.706) e: spare bits for international use. access to received information via bits rsp.rs13 and rsp.rs15. transmission is enabled via bits x sp. x s13 and x sp. x s15. additionally, automatic transmission for submultiframe error indication is selectable. s a : spare bits for national use. additionally, sa bit access via registers rsa 4 ? 8 and x sa 4 ? 8 is provided. hdlc-signaling in bits sa 4 -sa 8 is selectable. c 1 ?c 4 : cyclic redundancy check bits. a: remote alarm indication. additionally, automatic transmission of the a-bit is selectable. table 19 crc-multiframe structure (e1) sub- multiframe frame number bits1to8oftheframe 123456 78 multiframe i 0 1 2 3 4 5 6 7 c 1 0 c 2 0 c 3 1 c 4 0 0 1 0 1 0 1 0 1 0 a 0 a 0 a 0 a 1 s a 4 1 s a 4 1 s a 4 1 s a 4 1 s a5 1 s a5 1 s a5 1 s a5 0 s a61 0 s a62 0 s a63 0 s a6 4 1 s a7 1 s a7 1 s a7 1 s a7 1 s a 8 1 s a 8 1 s a 8 1 s a 8 ii 8 9 10 11 12 13 1 4 15 c 1 1 c 2 1 c 3 e * c 4 e * 0 1 0 1 0 1 0 1 0 a 0 a 0 a 0 a 1 s a 4 1 s a 4 1 s a 4 1 s a 4 1 s a5 1 s a5 1 s a5 1 s a5 0 s a61 0 s a62 0 s a63 0 s a6 4 1 s a7 1 s a7 1 s a7 1 s a7 1 s a 8 1 s a 8 1 s a 8 1 s a 8
peb 2255 falc-lh v1.3 functional description e1 data sheet 8 7 2000-07 for transmit direction, contents of time slot 0 are additionally determined by the selected transparent mode (see also figure 25 ): the crc procedure is automatically invoked when the multiframe structure is enabled. crc errors in the received data stream are counted by the 16 bit crc error counter cec (one error per submultiframe, maximum). additionally a crc 4 error interrupt status isr0.crc 4 may be generated if enabled by imr0.crc 4 . all crc bits of one outgoing submultiframe are automatically inverted in case a crc error is flagged for the previous received submultiframe. this function is enabled via bit rc0.crci. setting the bit rc0. x crci inverts the crc bits before transmission to the distant end. the function of rc0. x crci and rc0.crci are logically ored. 4.4.3.1 synchronization procedure multiframe alignment is assumed to have been lost if doubleframe alignment has been lost (flagged on status bit frs0.lfa). the rising edge of this bits causes an interrupt. the multiframe resynchronization procedure starts when doubleframe alignment has been regained which is indicated by an interrupt status bit isr2.far. for doubleframe synchronization refer to section doubleframe format. it may also be invoked by the user by setting bit fmr0.frs for complete doubleframe and multiframe re-synchronization bit fmr1.mfcs for multiframe re-synchronization only. the crc checking mechanism is enabled after the first correct multiframe pattern has been found. however, crc errors are not counted in asynchronous state. table 20 transmit transparent mode (crc multiframe e1) transmit transparent source for enabled by framing + crc abit sabits ebits ? x sp.tt0 tswm.tsif tswm.tsis tswm.tra tswm.tsa 4 ? 8 (int. generated) via pin x di 1) via pin x di via pin x di (int. generated) (int. generated) 1) pin x di or x sig or x fifo buffer (signaling controller) x sw. x ra 2) via pin x di x sw. x ra 1) x sw. x ra 1) via pin x di x sw. x ra 1) 2) automatic transmission of the a-bit is selectable x sw. xy 0? 4 3) via pin x di x sw. xy 0? 4 2) x sw. xy 0? 4 2) x sw. xy 0? 4 2) via pin x di 3) the s a -bit register x sa 4 - 8 may be used optionally x sp. x s13/ x s15 4 ) via pin x di (int. generated) via pin x di x sp. x s13/ x s15 3) x sp. x s13/ x s15 3) 4 ) additionally, automatic transmission of submultiframe error indication is selectable
peb 2255 falc-lh v1.3 functional description e1 data sheet 88 2000-07 in doubleframe asynchronous state, counting of framing errors, crc 4 bit errors and detection of remote alarm is stopped. ais is automatically sent to the backplane interface (can be disabled via bit fmr2.dais). further on the updating of the registers rsa6s and rs1-16 is halted (remote alarm indication, s a /s i -bit access). the multiframe synchronous state is established after detecting two correct multiframe alignment signals at an interval of n 2ms (n = 1, 2, 3 ?). the loss of multiframe alignment flag frs0.lmfa is reset. additionally an interrupt status multiframe alignment recovery bit isr2.mfar is generated with the falling edge of bit frs0.lmfa. 4.4.3.2 automatic force resynchronization (e1) in addition, a search for doubleframe alignment is automatically initiated if two multiframe pattern with a distance of n 2 ms have not been found within a time interval of 8 ms after doubleframe alignment has been regained (bit fmr1.afr). a new search for frame alignment is started just after the previous frame alignment signal. 4.4.3.3 floating multiframe alignment window (e1) after reaching doubleframe synchronization a 8 ms timer is started. if a multiframe alignment signal is found during the 8 ms time interval the internal timer is reset to remaining 6 ms in order to find the next multiframe signal within this time. if the multiframe signal is not found for a second time an interrupt status isr0.t 8 ms is provided. this interrupt usually occurs every 8 ms until multiframe synchronization is achieved. 4.4.3.4 crc4 performance monitoring (e1) in the synchronous state checking of multiframe pattern is disabled. however, with bit fmr2.almf an automatic multiframe resynchronization mode can be activated. if 9 15 out of 1000 errored crc submultiframes are found then a false frame alignment is assumed and a search for double- and multiframe pattern is initiated. the new search for frame alignment is started just after the previous basic frame alignment signal. 4.4.3.5 modified crc4 multiframe alignment algorithm (e1) the modified crc 4 multiframe alignment algorithm allows an automatic interworking between framers with and without a crc 4 capab ility. the interworking is realized as it is described in it u -t g.706 appendix b and shown in figure 4.5 on page 93 . if doubleframe synchronization is consistently present but crc 4 multiframe alignment is not achieved within 4 00 ms it is assumed that the distant end is initialized to doubleframe format. the crc 4 to non-crc 4 interworking is enabled via fmr2.rfs1/0 = 11 and is activated only if the receiver has lost its synchronization. if doubleframe alignment (basic frame alignment) is established a 4 00 ms timer and searching for multiframe alignment is started. a research for basic frame alignment is initiated if the crc 4 multiframe
peb 2255 falc-lh v1.3 functional description e1 data sheet 89 2000-07 synchronization could not be achieved within 8 ms and is started just after the previous frame alignment signal. the research of the basic frame alignment is done in parallel and is independent of the synchronization procedure of the primary basic frame alignment signal. during the parallel search all receiver functions are based on the primary frame alignment signal, like framing errors, s a -, s i -, a-bits ?). all subsequent multiframe searches are associated with each basic framing sequence found during the parallel search. if the crc 4 multiframe alignment sequence was not found within the time interval of 4 00 ms, the receiver is switched into a non-crc 4 mode indicated by setting the bit frs0.nmf (no multiframing found) and isr2.t 4 00ms. in this mode checking of crc bits is disabled and the received e-bits are forced to low. the transmitter framing format is not changed. even if multiple basic fas resynchronizations have been established during the parallel search, the receiver is maintained to the initially determined primary frame alignment signal location. however, if the crc 4 multiframe alignment could be achieved within the 4 00 ms time interval assuming a crc 4 to crc 4 interworking, then the basic frame alignment sequence associated to the crc 4 multiframe alignment signal is chosen. if necessary, the primary frame alignment signal location is adjusted according to the multiframe alignment signal. the crc 4 performance monitoring is started if enabled by fmr2.almf and the received e-bits are processed in accordance with it u -t g.70 4 . switching into the doubleframe format (non crc 4 ) mode after 4 00mscanbedisabled by setting of fmr3.e x tiw. in this mode the falc ? -lh continues search for multiframing. in the interworking mode setting of bit fmr1.afr is not allowed. 4.4.3.6 a-bit access (e1) if the falc ? -lh detects a remote alarm indication (bit 2 in ts0 not containing the fas word) in the received data stream the interrupt status bit isr2.ra is set. with the deactivation of the remote alarm the interrupt status bit isr2.rar is generated. by setting fmr2.a x ra the falc ? -lh automatically transmits the remote alarm bit = 1 in the outgoing data stream if the receiver detects a loss of frame alignment (frs0.lfa = 1). if the receiver is in synchronous state (frs0.lfa = 0) the remote alarm bit is reset in the outgoing data stream. additionally, if bit fmr3.e x tiw is set and the multiframe synchronous state could not be achieved within the 4 00 ms after finding the primary basic framing, the a-bit is transmitted active high to the remote end until the multiframing is found. note: the a-bit may be processed via the system interface. setting bit tswm.tra enables transparency for the a bit in transmit direction (refer to table 20 ).
peb 2255 falc-lh v1.3 functional description e1 data sheet 9 0 2000-07 4.4.3.7 s a - bit access (e1) due to signaling procedures using the five s a bits (s a 4 ?s a 8 )ofeveryotherframeofthe crc multiframe structure, three possibilities of access via the microprocessor are implemented. the standard procedure allows reading/writing the s a -bit registers rsw, x sw without further support. the s a -bit information is updated every other frame. the advanced procedure, enabled via bit fmr1.ensa, allows reading/writing the s a - bit registers rsa 4 ? 8 , x sa 4 ? 8 . a transmit or receive multiframe begin interrupt (isr0.rmb or isr1. x mb) is provided. registers rsa 4 - 8 contains the service word information of the previously received crc- multiframe or 8 doubleframes (bit slots 4 - 8 of every service word). these registers are updated with every multiframe begin interrupt isr0.rmb. with the transmit multiframe begin an interrupt isr1. x mb is generated and the contents of this registers x sa 4 - 8 are copied into shadow registers. the contents is subsequently sent out in the service words of the next outgoing crc multiframe (or every doubleframes) if none of the time slot 0 transparent modes is enabled. the transmit multiframe begin interrupt x mb request that these registers should be serviced. if requests for new information is ignored, current contents is repeated. the extended access via the receive and transmit fifos of the signaling controller. in this mode it is possible to transmit/receive a hdlc frame or a transparent bit stream in any combination of the s a bits. enabling is done by setting of bit ccr1.eits and the corresponding bits x c0.sa 8 e- 4 e/tswm.tsa 8 - 4 and resetting of registers ttr1- 4 ,rtr1- 4 and fmr1.ensa. the access to and from the fifos is supported by isr0.rme,rpf and isr1. x pr,als. sa6-bit detection according to ets 300233 four consecutive received sa6-bits are checked on the by ets 300233 defined sa6-bit combinations. the falc ? -lh detects following fixed sa6-bit combinations: sa61, sa62, sa63,sa6 4= 1000 ; 1010 ; 1100 ; 1110 ; 1111. all other possible 4 -bit combinations are grouped to status ? x ?. a valid sa6-bit combination must occur three times in a row. the corresponding status bit in register rsa6s is set. register rsa6s is from type ?clear on read?. with any change of state of the sa6-bit combinations an interrupt status isr0.sa6sc is generated. during the basic frame asynchronous state updating of register rsa6s and interrupt status isr0.sa6sc is disabled. in multiframe format the detection of the sa6-bit combinations can be done either synchronous or asynchronous to the submultiframe (fmr3.sa6s y ). in synchronous detection mode updating of register rsa6s is done in the multiframe synchronous state (frs0.lmfa = 0). in asynchronous detection mode updating is independent to the multiframe synchronous state.
peb 2255 falc-lh v1.3 functional description e1 data sheet 9 1 2000-07 sa6 bit error indication counters the sa6 bit error indication counter crc2l/h (16 bits) counts the received sa6 bit sequence 0001 or 0011 in every crc submultiframe. in the primary rate access digital section this counter option gives information about crc errors reported from the te via sa6 bit. incrementing is only possible in the multiframe synchronous state. the sa6 bit error indication counter crc3l/h (16 bits) counts the received sa6 bit sequence 0010 or 0011 in every crc submultiframe. in the primary rate access digital section this counter option gives information about crc errors detected at t-reference point and reporting them via the sa6 bit. incrementing is only possible in the multiframe synchronous state. 4.4.3.8 e-bit access (e1) due to signaling requirements, the e bits of frame 13 and frame 15 of the crc multiframe can be used to indicate received errored submultiframes: submultiframe i status e- bit located in frame 13 submultiframe ii status e- bit located in frame 15 no crc error: : e = 1 crc error: : e = 0 standard procedure after reading the submultiframe error indication rsp.si1 and rsp.si2, the microprocessor has to update contents of register x sp ( x s13, x s15). access to these registers has to be synchronized with transmit or receive multiframe begin interrupts (isr0.rmb or isr1. x mb). automatic mode in the multiframe synchronous state the e-bits are processed according to it u -t g.70 4 independently of bit x sp.ebp (e-bit polarity selection). by setting bit x sp.a x s status information of received submultiframes is automatically inserted in the e-bit position of the outgoing crc multiframe without any further interventions of the microprocessor. in the doubleframe and multiframe asynchronous state the e-bits are set or cleared, depending on the setting of bit x sp.ebp. submultiframe error indication counter the ebc (e-bit) counter ebcl and ebch (16 bits) counts zeros in e-bit position of frame 13 and 15 of every received crc multiframe. this counter option gives information about the outgoing transmit pcm line if the e bits are used by the remote end
peb 2255 falc-lh v1.3 functional description e1 data sheet 9 2 2000-07 for submultiframe error indication. incrementing is only possible in the multiframe synchronous state. note: e-bits may be processed via the system interface. setting bit tswm.tsis enables transparency for e bits in transmit direction (refer to table 20 ). figure 26 crc4 multiframe alignment recovery algorithms itd10310 out of primary bfa: inhibit incoming crc-4 performance monitoring reset all timers set frs0.lfa/lmfa/nmf = 110 no bfa search ? primary yes reset internal frame alignment status start 400 ms timer in primary bfa: enable primary bfa loss checking process (frs0.lfa = 0) start 8 ms timer can crc-4 mfa be found yes in 8 ms ? 400 ms timer elapsed ? yes no parallel bfa search good ? no no assume crc-4 to crc-4 interworking: confirm primary bfa associated with crc-4 mfa reset internal multiframe alignment status adjust primary bfa if necessary (frs0.lmfa = 0) confirm primary bfa set internal 400 ms timer expiration status bit assume crc-4 to non crc-4 interworking: (frs0.nmf = 1) start crc-4 performance monitoring yes or lfa ? error count crc-4 no continue crc-4 performance monitoring _ < 915 yes crc-4 mfa search
peb 2255 falc-lh v1.3 functional description e1 data sheet 9 3 2000-07 4.5 additional functions (e1) 4.5.1 error performance monitoring and alarm handling alarm indication signal: detection and recovery is flagged by bit frs0.ais and isr2.ais. transmission is enabled via bit fmr1. x ais. loss of signal: detection and recovery is flagged by bit frs0.los and isr2.los. remote alarm indication: detection and release is flagged by bit frs0.rra, rsw.rra and isr2.ra/rar. transmission is enabled via bit x sw. x ra. ais in time slot 16: detection and release is flagged by bit frs1.ts16ais and isr3.ais16. transmission is enabled by writing all ones in registers x s1-16. los in time slot 16: detection and release is flagged by bit frs1.ts16los. transmission is enabled by writing all zeros in registers x s1-16. remote alarm in time slot 16: detection and release is flagged by bit frs1.ts16ra and isr3.ra16. transmission is enabled via bit ccr1. x ts16ra or x s1.2. transmit line shorted: detection and release is flagged by bit frs1. x ls and isr1. x lsc. transmit ones density: detection and release is flagged by bit frs1. x lo and isr1. x lsc. table 21 summary of alarm detection and release (e1) alarm detection condition clear condition loss of signal (los) no transitions (logical zeros) in a programmable time interval of 16... 4 0 9 6 consecutive pulse periods. programmable receive input signal threshold programmable number of ones (1-256) in a programmable time interval of 16... 4 0 9 6 consecutive pulse periods. a one is a signal with a level above the programmed threshold. alarm indication signal (ais) fmr0.alm = 0: less than 3 zeros in 250 s and loss of frame alignment declared fmr0.alm = 1: less than 3 zeros in each of two consecutive 250 s periods fmr0.alm = 0: more than 2 zeros in 250 s fmr0.alm = 1: more than 2 zeros in each of two consecutive 500 s periods remote alarm (rra) bit 3 = 1intimeslot0not containing the fas word set conditions no longer detected.
peb 2255 falc-lh v1.3 functional description e1 data sheet 94 2000-07 4.5.2 auto modes automatic remote alarm access if the receiver has lost its synchronization a remote alarm can be sent automatically, if enabled by bit fmr2.a x ra to the distant end. the remote alarm bit is set automatically in the outgoing data stream if the receiver is in asynchronous state (frs0.lfa bit is set). in synchronous state the remote alarm bit is removed. automatic e bit access by setting bit x sp.a x s status information of received submultiframes is automatically inserted in e-bit position of the outgoing crc multiframe without any further interventions of the microprocessor. automatic ais to system interface in asynchronous state the synchronizer enforces automatically an ais to the receive system interface. however, received data can be transparently switched through if bit fmr2.dais is set. remote alarm in time slot 16 (ts16ra) y -bit = 1receivedincas multiframe alignment word y -bit = 0receivedincas multiframe alignment word loss of signal in time slot 16 (ts16los) all zeros for at least 16 consecutively received time slots 16 receiving a one in time slot 16 alarm indication signal in time slot 16 (ts16ais) time slot 16 containing less than 4 zeros in each of two consecutive cas multiframes periods time slot 16 containing more than 3 zeros in each of two consecutive cas multiframes periods transmit line short ( x ls) if x l1 and x l2 are shortened for at least 32 pulses ; pins x l1 and x l2 are forced into a high impedance state automatically, if bit x pm2.da x lt is reset. after 32 consecutive pulse periods the outputs x l1/2 are activated again and the internal transmit current limiter is checked. if a short between x l1/ 2 is still existing, the outputs x l1/ 2 are switched into high impedance state again. when the short disappears pins x l1/2 are activated automatically. transmit ones density ( x lo) 32 consecutive zeros in the transmit data stream on x l1/2 cleared with each transmitted pulse table 21 summary of alarm detection and release (e1) (cont?d) alarm detection condition clear condition
peb 2255 falc-lh v1.3 functional description e1 data sheet 9 5 2000-07 automatic clock source switching in slave mode (lim0.mas = 0) the dco-r synchronizes to the recovered route clock. in case of loss of signal los the dco-r switches automatically to master mode. automatic freeze signaling: u pdating of the received signaling information is controlled by the freeze signaling status. optionally automatic freeze signaling can be disabled by setting bit sic3.daf. 4.5.3 error counter the falc ? -lh offers six error counters each of them has a length of 16 bit. they record code violations, framing bit errors, e-bit errors, crc 4 bit errors and crc 4 error events which are flagged in the different sa6 bit combinations. each of the error counter is buffered. u pdating the buffer is done in two modes: one second accumulation on demand via handshake with writing to the dec register in the one second mode an internal one second timer updates these buffers and reset the counter to accumulate the error events in the next one second period. the error counter can not overflow. error events occurring during reset are not lost. 4.5.4 errored second the falc ? -lh supports the error performance monitoring by detecting the following alarms or error events in the received data: framing errors, crc errors, code violations, loss of frame alignment, loss of signal, alarm indication signal, e bit error, receive and transmit slips. with a programmable interrupt mask register imr 4 all these alarms or error events can generate an errored second interrupt (isr3.es) if enabled. 4.5.5 second timer additionally a one second timer interrupt is generated internally to indicate that the enabled alarm status bits or the error counters have to be checked. the clock is derived from signal rcl k . 4.5.6 in-band loop generation and detection the falc ? -lh generates and detects a framed or unframed in-band loop up/activate and down/deactivate pattern with bit error rates up to1/100. framed or unframed in-band loop code is selected by lcr1.fllb. replacing transmit data with the in-band loop codes is done by fmr3. x ld/ x l u . the falc ? -lh also offers the ability to generate and detect a flexible in-band loop up and down pattern (if lcr1.llbp = 1) or a default pattern 00001 for up and 001 for down (if lcr1.llbp = 0).
peb 2255 falc-lh v1.3 functional description e1 data sheet 9 6 2000-07 the user defined loop up and loop down pattern is programmable individually from 2 to 8 bit in length (lcr1.lac1/0 and lcr1.ldc1/0). programming of loop codes is done in registers lcr2 and lcr3. status and interrupt status bits inform the user whether a loop up or loop down code was detected. 4.5.7 time slot 0 transparent mode the transparent modes are useful for loopbacks or for routing data unchanged through the falc ? -lh. in receive direction, transparency for ternary or dual/single rail unipolar data is always achieved if the receiver is in the synchronous state. in asynchronous state the data may be transparently switched through if bit fmr2.dais is set. however, correct time slot assignment can not be guaranteed due to missing frame alignment between line and system side. setting of bit fmr2.rtm disconnects control of the internal elastic store from the receiver. the elastic buffer is now in a ?free running? mode without any possibility to update the time slot assignment to a new frame position in case of re-synchronization of the receiver. together with fmr2.dais this function can be used to realize undisturbed transparent reception. transparency in transmit direction can be achieved by activating the time slot 0 transparent mode (bit x sp.tt0 or tswm.7-0). if x sp.tt0 = 1 all internal information of the falc ? -lh (framing, crc, s a /s i bit signaling, remote alarm) is ignored. with register tswm the s i -bits, a-bit or the s a 4 - 8 bits can be selectively enabled to send data transparent from port x di to the far end. for complete transparency the internal signaling controller, idle code generation and ais alarm generation, single channel and payload loop back has to be disabled.
peb 2255 falc-lh v1.3 functional description e1 data sheet 9 7 2000-07 4.6 test functions (e1) 4.6.1 pseudo-random bit sequence generation and monitor the falc ? -lh has the ability to generate and monitor 2 15 -1 and 2 20 -1 pseudo-random bit sequences (prbs). the generated prbs pattern is transmitted optionally inverted or not to the remote end via pins x l1/2 or x dop/n. generating and monitoring of prbs pattern is done according to it u -t o. 151. the prbs monitor senses the prbs pattern in the incoming data stream. synchronization is done on the inverted and non inverted prbs pattern. the current synchronization status is reported in status and interrupt status registers. enabled by bit lcr1.eprm each prbs bit error increments an error counter (cec2). synchronization is reached within 4 00 ms with a probability of 99 . 9% and a bit error rate of 1/10. if an ?all 0? or ?all 1? signal is detected, synchronous state is indicated, too. 4.6.2 remote loop in the remote loopback mode the clock and data recovered from the line inputs rl1/2 or rdip/rdin are routed back to the line outputs x l1/2 or x dop/ x don via the analog or digital transmitter. as in normal mode they are also processed by the synchronizer and then sent to the system interface.the remote loopback mode is selected by setting the respective control bits lim1.rl + jatt. received data may be looped with or without the transmit jitter attenuator (fifo = jatt). figure 27 remote loop (e1) its09750 rdo xdi rclk rl1 rl2 xl1 xl2 fifo xclk rclk dco1/2 framer rec. framer trans. store elast. elast. store recovery data clock + mux mux
peb 2255 falc-lh v1.3 functional description e1 data sheet 98 2000-07 4.6.3 payload loop back to perform an effective circuit test a payload loop is implemented. the payload loop back (fmr2.plb) loops the data stream from the receiver section back to transmitter section. the looped data passes the complete receiver including the wander and jitter compensation in the receive elastic store and were output on pin rdo. instead of the data an ais (fmr2.sais) can be sent to the system interface. the framing bits, crc 4 and spare bits are not looped, if x sp.tt0 = 0. they are originated by the falc ? -lh transmitter. if the plb is enabled the transmitter and the dataonpins x l1/2 or x dop/ x don are clocked with scl k r/rcl k instead of scl kx . if x sp.tt0 = 1 the received time slot 0 is sent transparently back to the line interface. data on the following pins are ignored: x di, x sig, scl kx ,s y p x and x mfs. all the received data is processed normally. figure 28 payload loop (e1) note: returned data is not multiframe synchronous. its09748 clock + data rec. framer elast. store trans. framer rdo xdi rclk rl1 rl2 xl1 xl2 recovery sclkx sclkr mux ais-gen elast. store
peb 2255 falc-lh v1.3 functional description e1 data sheet 99 2000-07 4.6.4 local loop the local loopback mode, selected by lim0.ll = 1, disconnects the receive lines rl1/2 or rdip/rdin from the receiver. instead of the signals coming from the line the data provided by system interface are routed through the analog receiver back to the system interface. however, the bit stream is transmitted undisturbedly on the line. however an ais to the distant end can be enabled by setting fmr1. x ais without influencing the data looped back to the system interface. note that enabling the local loop usually invokes an out of frame error until the receiver can resynchronize with the new framing. the serial codes for transmitter and receiver have to be identical. in digital interface nr z mode, a clock must be provided on pin rcl k i( = rl2) to enable switching into local loop mode. figure 29 local loop (e1) its09749 rdo xdi rclk ais-gen rl1 rl2 xl1 xl2 framer rec. framer trans. store elast. recovery data clock + mux elast. store
peb 2255 falc-lh v1.3 functional description e1 data sheet 100 2000-07 4.6.5 single channel loop back each of the 32 time slots may be selected for loopback from the system pcm input ( x di) to the system pcm output (rdo). this loopback is programmed for one time slot at a time selected by register loop. during loopback, an idle channel code programmed in register idle is transmitted to the remote end in the corresponding pcm route time slot. for the time slot test, sending sequences of test patterns like a 1 khz check signal should be avoided. otherwise, an increased occurrence of slips in the tested time slot disturbs testing. these slips do not influence the other time slots and the function of the receive memory. the usage of a quasi-static test pattern is recommended. figure 30 single channel loopback (e1) its09747 rdo xdi rclk rl1 rl2 xl1 xl2 idle code framer trans. framer rec. store elast. store elast. mux mux recovery data clock +
peb 2255 falc-lh v1.3 functional description e1 data sheet 101 2000-07 4.6.6 alarm simulation (e1) alarm simulation does not affect the normal operation of the device, i.e. all time slots remain available for transmission. however, possible ?real? alarm conditions are not reported to the processor when the device is in the alarm simulation mode. the alarm simulation is initiated by setting the bit fmr0.sim. the following alarms are simulated: loss of signal alarm indication signal (ais) loss of pulse frame remote alarm indication receive and transmit slip indication framing error counter code violation counter (hdb3 code) crc 4 error counter e-bit error counter cec2 counter cec3 counter some of the above indications are only simulated if the falc ? -lh is configured in a mode where the alarm is applicable (e.g. no crc 4 error simulation when doubleframe format is enabled). setting of the bit fmr0.sim initiates alarm simulation, interrupt status bits is set. error counting and indication occurs while this bit is set. after it is reset all simulated error conditions disappear, but the generated interrupt statuses are still pending until the corresponding interrupt status register is read. alarms like ais and los are cleared automatically. interrupt status register and error counters are automatically cleared on read.
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 102 2000-07 5 functional description t1/j1 5.1 receive path in t1/j1 mode figure 31 receive clock system (t1/j1) receive line interface (t1/j1) for data input, three different data types are supported: ternary coded signals received at multifunction ports rl1 and rl2 from a -10 db (short haul, lim0.e q on = 0) or -36 db (long haul, lim0.e q on = 1) ternary interface. the ternary interface is selected if lim1.drs is reset. digital dual rail signals received on ports rdip and rdin. the dual rail interface is selected if lim1.drs and fmr0.rc1 is set. u nipolar data on port roid received from a fiber optical interface. the optical interface is selected if lim1.drs is set and fmr0.rc1...0 = 00. alternatively the optical interface can be switched to pin 6 8 ( x mfb/ x oid) and pin 8 0 (roid) by setting bit loop.spn. equalizer clock & data recovery dpll line decoder alarm detector analog los detector dco-r pd osc. rate converter x tal1 16.3 84 mhz cl k 16m cl k8 m cl kx fsc rl1 / rdip / roid rl2 / rdin / rcl k i rdata rcl k f0048
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 103 2000-07 receive short and long haul interface (t1/j1) the falc ? -lh has now an integrated short-haul and long-haul line interface, consisting of a receive equalization network, noise filtering and programmable line build-outs (lbo). 5.1.1 receive equalization network (t1/j1) the falc ? -lh automatically recovers the signals received on pins rl1/2 in a range of up to -36 db. the maximum reachable length with a 22 awg twisted-pair cable is 2000 m. after reset the falc ? -lh is in ?short haul? mode, received signals are recovered up to -10 db of cable attenuation. switching in ?long haul? mode is done by setting of register lim0.e q on. the integrated receive equalization network recovers signals with up to -36 db of cable attenuation. noise filters eliminate the higher frequency part of the received signals. the incoming data is peak detected and sliced at 55 % of the peak value to produce the digital data stream. the received data is then forwarded to the clock & data recovery unit. 5.1.2 receive line attenuation indication (t1/j1) status register res reports the current receive line attenuation in a range of 0 to -36 db in 25 steps of approximately 1. 4 db each. the least significant 5 bits of this register indicate the cable attenuation in db. these 5 bits are only valid in conjunction with the two most significant bits (res.ev1/0 = 01). 5.1.3 receive clock and data recovery (t1/j1) the analog received signal on port rl1/2 is equalized and then peak-detected to produce a digital signal. the digital received signal on port rdip/n is directly forwarded to the dpll. the receive clock and data recovery extracts the route clock rcl k from the data stream received at the rl1/2, rdip/rdin or roid lines and converts the data stream into a single rail, unipolar bit stream. normally the clock that is output via pin rcl k is the recovered clock from the signal provided by rl1/2 or rdip/n has a duty cyclecloseto50 % . the free run frequency is defined by x tal3 divided by 8 in periods with no signal. the intrinsic jitter generated in the absence of any input jitter is not more than 0.035 u i. in digital bipolar line interface mode the clock and data recovery accepts only b 8z s or ami coded signals with 50 % duty cycle. 5.1.4 receive line coding (t1/j1) the b 8z s line code or the ami ( z cs) coding is provided for the data received from the ternary or the dual rail interface. all code violations that do not correspond to zero substitution rules are detected. the detected errors increment the code violation counter (16 bits length). in case of the optical interface mode nr z coding is performed automatically and data is latched with the falling edge of pin rcl k i. when using the
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 10 4 2000-07 optical interface with nr z coding, the decoder is by-passed and no code violations are detected. additionally, the receive line interface contains the alarm detection for alarm indication signal ais (blue alarm) and the loss of signal los (red alarm). pulse density violations are detected and indicated via bit frs1.pden. the signal at the ternary interface is received at both ends of a transformer. figure 32 receiver configuration (t1/j1) 5.1.5 loss of signal detection (t1/j1) there are different definitions for detecting loss of signal alarms (los) in the it u -t g.775 and at & ttr5 4 016. the falc ? -lh covers all these standards. the los indication is performed by generating an interrupt (if not masked) and activating a status bit. additionally a los status change interrupt is programmable via register ipc.sci. detection: an alarm is generated if the incoming data stream has no pulses (no transitions) for a certain number (n) of consecutive pulse periods. ?no pulse? in the digital receive interface means a logical zero on pins rdip/rdin/roid. a pulse with an amplitude less than q db below nominal is the criteria for ?no pulse? in the analog receive interface (lim1.drs = 0). in short haul mode (lim0.e q on = 0), the receive signal level q is programmable via three control bits lim1.ril2...0 in a range of about 1 4 00 to 200 mv differential voltage between pins rl1/2 (see chapter 11.3 on page 357 ). in long table 22 recommended receiver configuration values (t1/j1) parameter characteristic impedance 100 ? 110 ? t1 j1 r 2 ( 1 % ) [ ? ] 200 220 t 2 : t 1 1: 1: its10967 line t 2 t 1 rl2 rl1 2 r r falc 2 2
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 105 2000-07 haul mode (lim0.e q on = 1) the analog los criteria is defined by the equalizer status. the number n may be set via a 8 bit register pcd. the contents of the pcd register is multiplied by 16, which results in the number of pulse periods, or better, the time which has to suspend until the alarm has to be detected. the range therefore results from 16 to 4 0 9 6 pulse periods. recovery: in general the recovery procedure starts after detecting a logical ?one? (digital receive interface) or a pulse (analog receive interface) with an amplitude more than q db (defined by lim1.ril2...0) of the nominal pulse. the value in the 8 bit register pcr defines the number of pulses (1 to 255) to clear the los alarm. additional recovery conditions may be programmed by register lim2. note: in long haul mode, los alarm is declared either if ? no pulses ? are detected for the period defined in pcd or the signal level drops below typically about -35 db of the nominal signal ( ? low signal level ? ). additionally, the incoming data stream is cleared, if this ? low signal level ? is detected in order to generate a fixed data stream before first bit errors occur. typically, this loss of signal threshold is about -36 db. because the ds1 signal varies at 3.0v +/ - 20%, this loss of signal threshold correlates directly to the transmitted pulse amplitude. it changes to -33 db, if the generated maximum transmit amplitude at the remote end is not more than 2.4v for recovery this means, that at first the signal level has to increase and then the pulses are counted and compared to pcr to return from los indication. please also note, that this behavior is slightly different to falc-lh v1.1. 5.1.6 receive jitter attenuator (t1/j1) the receive jitter attenuator is placed in the receive path. the jitter attenuator meets the requirements of p u b62 4 11, p u b 4 3 8 02, tr-ts y 00 9 ,tr-ts y 253, tr-ts y 499 and it u -t i. 4 31, g.703 and g. 8 2 4 . the internal dco-r generates a ?jitter free? output clock which is directly dependent on the phase difference of the incoming clock and the jitter attenuated clock. the receive jitter attenuator can be either synchronized with the extracted receive clock rcl k or to a1.5 44 or 2.0 48 -mhz clock provided on pin s y nc. received data are written into the receive elastic buffer with rcl k and are read out with scl k r. optionally an 8 khz clock is provided on pin x cl k /fsc or fsc . the dco-r circuitry attenuates the incoming jittered clock starting at 6 hz jitter frequency with 20 db per decade fall off. wander with a jitter frequency below 6 hz is passed unattenuated. the intrinsic jitter in the absence of any input jitter is < 0.02 u i.
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 106 2000-07 for some applications it might be useful starting of jitter attenuation at lower frequencies. therefore the corner frequency is switchable by the factor of ten down to 0.6 hz (lim2.scf). jitter attenuation can be achieved either using an external tunable crystal on pins x tal1/ x tal2 or using the crystal-less jitter attenuation selected by lim2.dja1/2. in this case, a stable clock or regular crystal of 16.3 84 mhz has to be provided on pin x tal1 ( + /- 50 ppm). in crystal-less mode the system clock output on pin cl k 16m can be either the dejittered or the non-dejittered clock (lim3.csc). the dco-r circuitry is automatically centered to the nominal bit rate if the reference clock on pin s y nc/rcl k ismissedfortwo2.0 48 or 1.5 44 -mhz clock periods. in analog line interface mode the rcl k is always running. only in digital line interface mode with single rail data (nr z ) a gapped clock on pin rcl k may occur. the receive jitter attenuator works in two different modes: slave mode in slave mode (lim0.mas = 0) the dco-r is synchronized with the recovered route clock. in case of los the dco-r switches to master mode automatically. master mode in master mode (lim0.mas = 1) the jitter attenuator is in free running mode if on pin s y nc no clock is supplied. if an external clock on the s y nc input is applied, the dco- r synchronizes to this input. the external frequency can be 1.5 44 mhz (lim1.dcoc = 0) or 2.0 48 mhz (lim1.dcoc = 1). the following table shows the clock modes with the corresponding synchronization sources. table 23 system clocking (t1/j1) mode internal los active sync input system clocks master independent fixed to vss free running (oscillator centered) master independent 1.5 44 mhz synchronized with s y nc input (lim1.dcoc = 0) master independent 2.0 48 mhz synchronized with s y nc input (lim1.dcoc = 1) slave no fixed to vss synchronized with line rcl k slave no 1.5 44 mhz or 2.0 48 mhz synchronized with line rcl k
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 107 2000-07 the jitter attenuator meets the jitter transfer requirements of the p u b62 4 11, p u b 4 3 8 02, tr-ts y 00 9 ,tr-ts y 253, tr-ts y 499 ,i. 4 31 and g. 703.(refer to figure 33 ). figure 33 jitter attenuation performance (t1/j1) slave yes fixed to vss free running (oscillator centered) slave yes 1.5 44 mhz synchronized with s y nc (lim1.dcoc = 0) slave yes 2.0 48 mhz synchronized with s y nc (lim1.dcoc = 1) table 23 system clocking (t1/j1) (cont?d) mode internal los active sync input system clocks itd10314 1 -70 frequency attenuation -60 -50 -40 -30 -20 -10 0 10 10 100 1000 10000 100000 db hz slope slope - - 40 20 db/decade db/decade falc pub 62411_h pub 62411_l r
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 10 8 2000-07 5.1.7 jitter tolerance (t1/j1) the falc ? -lh receiver?s tolerance to input jitter complies to it u and bellcore requirements for t1 applications. figure 34 shows the curves of different input jitter specifications stated below as well as the falc ? -lh performance. figure 34 jitter tolerance (t1/j1) jitter amplitude jitter frequency 1 10 100 1000 10000 100000 hz u i 1 0.1 10 100 1000 p u b62 4 11 tr-nwt 000 499 cat ii ccitt g. 8 23 it u -t i. 4 31 falc ? f0025
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 10 9 2000-07 5.1.8 output jitter (t1/j1) according to the input jitter defined by p u b62 4 11 the falc ? -lh generates the output jitter, which is specified in table 24table below. 5.1.9 transmit jitter attenuator (t1/j1) the transmit jitter attenuator dco- x circuitry generates a ?jitter free? transmit clock and meets the following requirements: p u b62 4 11, p u b 4 3 8 02, tr-ts y 00 9 ,tr-ts y 253, tr-ts y 499 and it u -t i. 4 31 and g.703. the dco- x circuitry works internally with the same high frequency clock as the receive jitter attenuator it does. it synchronizes either to the working clock of the transmit backplane interface or the clock provided by pin s y nc2 (1.5 44 mhz if lim1.dcoc = 0or2.0 48 mhz if lim1.dcoc = 1) or the receive clock rcl k (remote loop with jatt/loop-timed). the dco- x attenuates the incoming jitter starting at 6 hz with 20 db per decade fall off. with the jitter attenuated clock, which is directly dependent on the phase difference of the incoming clock and the jitter attenuated clock, data is read from the transmit elastic buffer (2 frames) or from the jatt buffer (2 frames, remote loop with jatt) wander with a jitter frequency below 6 hz is passed transparently. the dco- x accepts gapped clocks which are used in atm or sdh/sonet applications. the jitter attenuated clock is output on pin x cl k . the transmit jitter attenuator can be disabled. in the loop-timed clock configuration (lim2.elt) the dco- x circuitry generates a transmit clock which is frequency synchronized with rcl k . in this configuration the transmit elastic buffer has to be enabled. table 24 output jitter (t1/j1) specification measurement filter bandwidth output jitter (ui peak to peak) lower cutoff upper cutoff p u b62 4 11 10 hz 8 khz < 0.02 8 khz 4 0khz < 0.02 10 hz 4 0khz < 0.02 broadband < 0.02
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 110 2000-07 figure 35 transmit clock system (t1/j1) note: dr = dual rail interface; dco-x = digital controlled oscillator transmit 5.1.10 framer/synchronizer (t1/j1) the following functions are performed: synchronization on pulse frame and multiframe error indication when synchronization is lost. in this case, ais is sent to the system side automatically and remote alarm to the remote end if en/disabled. initiating and controlling of resynchronization after reaching the asynchronous state. this can be done automatically by the falc ? -lh or user controlled via the microprocessor interface. detection of remote alarm (yellow alarm) indication from the incoming data stream. separation of service bits and data link bits. this information is stored in special status registers. detection of framed or unframed in band loop u p/down code generation of various maskable interrupt statuses of the receiver functions. d a pulse shaper framer elastic store x di dco- x pd osc. scl kx s y nc2 rcl k x cl k x tal3 12.352 mhz 6mhz 1.5mhz rate conv. f0049
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 111 2000-07 generation of control signals to synchronize the crc checker and the receive elastic buffer. if programmed and applicable to the selected multiframe format, crc checking of the incoming data stream is done by generating check bits for a crc multiframe according to the crc 6 procedure (refer to it u -t g.70 4 ). these bits are compared with those check bits that are received during the next crc multiframe. if there is at least one mismatch, the crc error counter (16 bit) is incremented. 5.1.11 receive elastic buffer (t1/j1) the received bit stream is stored in the receive elastic buffer. the memory is organized as a two-frame elastic buffer with a maximum size of 48 8 bit. the size of the elastic buffer can be configured independently for the receive and transmit direction. programming of the receive buffer size is done by sic1.rbs1/0 : rbs1/0 = 00 : two frame buffer or 3 84 bits maximum of wander amplitude (peak-to-peak): (1 u i = 6 48 ns ) system interface clocking rate: 8 .1 9 2mhz: 1 4 2 u i in channel translation mode 0 7 8u i in channel translation mode 1 system interface clocking rate: 1.5 44 mhz: max. wander: 126 u i average delay after performing a slip: 1 frame or 1 9 3bits rbs1/0 = 01 : one frame buffer or 1 9 3bits system interface clocking rate: 8 .1 9 2mhz: max. wander : 8 0 u i in channel translation mode 0 max. wander : 50 u i in channel translation mode 1 system interface clocking rate: 1.5 44 mhz: max. wander: 7 4u i average delay after performing a slip: 9 6bits rbs1/0 = 10 : short buffer or 9 6bits: system interface clocking rate: 8 .1 9 2mhz: max. wander : 2 8u i in channel translation mode 0 ; channel translation mode 1 not supported system interface clocking rate: 1.5 44 mhz: max. wander: 3 8u i average delay after performing a slip: 48 bits rbs1/0 = 11 : bypass of the receive elastic buffer the functions of the receive elastic buffer are: clock adaption between system clock (scl k r) and internally generated route clock (rcl k ). compensation of input wander and jitter.
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 112 2000-07 frame alignment between system frame and receive route frame reporting and controlling of slips controlled by special signals generated by the receiver, the unipolar bit stream is converted into bit-parallel, time slot serial data which is circularly written to the elastic buffer using the internally generated receive route clock (rcl k ). reading of stored data is controlled by the system clock sourced by scl k randthe synchronous pulse (s y pr ) in conjunction with the programmed offset values for the receive time slot/clock slot counters. after conversion into a serial data stream, the data is given out via port rdo. if the receive buffer is bypassed, data is clocked off with rcl k instead of scl k r. if 8 .1 9 2 mhz reference frequency is used, one of two channel translation modes has to be selected. the 2 4 received time slots (t1/j1) can be translated into the 32 system time slots (e1) in two different channel translation modes (selected by fmr1.ctm). u nequipped time slots are set to ?ff h ?. refer to table 26 . in one frame or short buffer mode the delay through the receive buffer is reduced to an average delay of 9 6or 48 bits. in this case s y pr to be programmed as input is not allowed. slips are performed in all buffer modes except the bypass mode. after a slip is detected the read pointer is adjusted to one half of the current buffer size. the following table gives an overview of the receive buffer operating mode. . table 25 receive buffer operating modes (t1/j1) sic1.rbs1...0 buffer size ts offset programing (rc1...0) slip performance 11 bypass 1) 1) in bypass mode the clock provided on pin scl k r is ignored. clocking is done with rcl k . rfm (s y pr = output) must be selected ; value of rc1...0 determines the position of rfm no slips 10 short buffer rfm (s y pr = output) must be selected ; value of rc1...0 determines the position of rfm yes 01 1 frame rfm (s y pr = output) must be selected ; value of rc1...0 determines the position of rfm yes 00 2 frames s y pr is input and determines the frame position together with rc1...0 offset. yes slips are performed on the frame boundary
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 113 2000-07 figure 36 gives an idea of operation of the receive elastic buffer: a slip condition is detected when the write pointer (w) and the read pointer (r) of the memory are nearly coincident, i.e. the read pointer is within the slip limits (s + ,s?).ifa slip condition is detected, a negative slip (one frame or one half of the current buffer size is skipped) or a positive slip (one frame or one half of the current buffer size is read out twice) is performed at the system interface, depending on the difference between rcl k and the current working clock of the receive backplane interface. i.e. on the position of pointer r and w within the memory. a positive/negative slip is indicated in the interrupt status bits isr3.rsp and isr3.rsn. figure 36 the receive elastic buffer as circularly organized memory table 26 channel translation modes (t1/j1) speech channels time slots c. translation mode 0 c. translation mode 1 fs/dl fs/dl 0 11 1 22 2 33 3 ? 44 limits for slip detection (mode dependent) read pointer (system clock controlled) write pointer (route clock controlled) r ? s+, s- r : : w: frame 2 time slots s- r frame 1 time slots moment of slip detection itd10952 w s+ slip
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 11 4 2000-07 -:ff h 4 55 56 6 67 7 ? 88 7 99 8 10 10 9 11 11 ?12 12 10 13 13 11 1 4 1 4 12 15 15 ?16 16 13 17 17 1 4 1 8 1 8 15 1 9 1 9 ?20 20 16 21 21 17 22 22 1 8 23 23 ?2 4 2 4 1 9 ?25 20 ? 26 21 ? 27 ?? 2 8 22 ? 2 9 23 ? 30 2 4 ?31 table 26 channel translation modes (t1/j1) (cont?d) speech channels time slots c. translation mode 0 c. translation mode 1
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 115 2000-07 5.1.12 receive signaling controller (t1/j1) the signaling controller may be programmed to operate in various signaling modes. the falc ? -lh performs the following signaling and data link methods. 5.1.12.1 hdlc/sdlc or lapd access in case of common-channel signaling the signaling procedure hdlc/sdlc or lapd according to q . 9 21 is supported. the signaling controller of the falc ? -lh performs the flag detection, crc checking, address comparison and zero bit-removing. the received data flow and the address recognition features may be performed in very flexible way, to satisfy almost any practical requirements. depending on the selected address mode, the falc ? -lh may perform a 1 or 2 byte address recognition. if a 2-byte address field is selected, the high address byte is compared with the fixed value feh or fch (group address) as well as with two individually programmable values in rah1 and rah2 registers. according to the isdn lapd protocol, bit 1 of the high byte address is interpreted as command/response bit (c/r) and is excluded from the address comparison. buffering of receive data is done in a 6 4 byte deep rfifo. in signaling controller transparent mode, fully transparent data reception without hdlc framing is performed, i.e. without flag recognition, crc checking or bit-stuffing. this allows user specific protocol variations. the falc ? -lh offers the flexibility to extract data during certain time slots. any combination of time slots may be programmed independently for the receive and transmit direction. 5.1.12.2 cas bit-robbing (t1/j1, serial access mode) the signaling information is carried in the lsb of every sixth frame for each time slot. the signaling controller samples the bit stream on the receive system side. the complete cas multiframe is transmitted on pin rsig. the signaling data is clocked out with the working clock of the receive highway in conjunction with the receive synchronization pulse (s y pr ). data on rsig is transmitted in the last 4 bits per time slot and are time slot aligned to the data on rdo. in esf format the a,b,c,d bits are placed in the bit positions 5- 8 per time slot. in f12/72 format the a and b bits are repeated in the c and d bit positions. the first 4 bits per time slot can be optionally fixed high or low. the fs/dl time slot is transmitted on rdo and rsig. during idle time slots no signaling information is transmitted. data on rsig are only valid if the freeze signaling status is inactive. with fmr1.sais an all ones may be transmitted on rdo and rsig. u pdate of the receive signaling information is controlled by the freeze signaling status. if signaling information is frozen updating of the registers rs1-16 is disabled. the freeze signaling status is output on pin rfsp /free z s and is generated, if: frs0.lfa/lmfa = 1or frs0.los = 1or
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 116 2000-07 a receive slip occurred 5.1.12.3 cas bit-robbing (t1/j1, p access mode) the signaling information is carried in the lsb of every sixth frame for each time slot. the signaling controller samples the bit stream on the receive line side. receive signaling data is stored in the registers rs1-12. to relieve the p load from always reading the complete rs1-12 buffer every 3 ms the falc ? -lh notifies the p via interrupt isr0.rsc only when signaling changes from one multiframe to the next. 5.1.12.4 bit oriented messages in esf-dl channel (t1/j1) the falc ? -lh supports the dl-channel protocol for esf format according to ansi t1. 4 03 specification or according to at & ttr5 4 016. the hdlc- and bit oriented message (bom)-receiver may be switched on/off independently. if the falc ? -lh is used for hdlc formats only, the bom receiver has to be switched off. if hdlc- and bom-receiver has been switched on (mode.hrac/brac), an automatic switching between hdlc and bom mode is enabled. if eight or more consecutive ones are detected, the bom mode is entered. u pon detection of a flag in the data stream, the falc ? -lh switches back to hdlc-mode. in bom-mode, the following byte format is assumed (the left most bit is received first): 111111110xxxxxx0 two different bom reception modes can be programmed (ccr1.brm). 5.1.12.5 data link access in f72 format (t1/j1) the dl-channel protocol is supported as follows: - access is done on a multiframe basis via registers rdl1-3, - the dl bit information from frame 26 to 72 is stored in the receive fifo of the signaling controller. 5.2 system interface in t1/j1 mode the interface to the receive system highway is realized by two data buses, one for the data rdo and one for the signaling data rsig. the receive highway is clocked via pin scl k r, while the interface to the transmit system highway is independently clocked via pin scl kx . the frequency of these working clocks and the data rate for the receive and transmit system interface is programmable by sic1.srsc and sic1.s x sc. transmit and receive clock frequencies have to be the same. selectable system clock and data rates and their valid combinations are shown in the table below.
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 117 2000-07 x = valid, -- = invalid generally the data or marker on the system interface are clocked off or latched on the falling edge of the scl k r/scl kx clock independently. the signal on pin s y pr in conjunction with the assigned timeslot offset in register rc0 and rc1 define the beginning of a frame on the receive system highway. thesignalonpins y p x in conjunction with the assigned timeslot offset in register x c0 and x c1 define the beginning of a frame on the transmit system highway. adjusting the frame begin (time slot 0, bit 0) relative to s y pr/ x is possible in the range of 0...125 sec. a receive frame marker rfm can be activated (sic2.srfso = 1) during any bit position of the entire frame. programming is done with registers rc1/0. the receive frame marker is active high for one 1.5 44 /2.0 48 mhz cycle and is clocked off with the falling edge of the clock which is input on port scl k r or rcl k . table 27 system clock and data rates (t1/j1) system data rate clock rate 1.544 mhz clock rate 8.192 mhz 1.5 44 mbit/s x -- 2.0 48 mbit/s -- x 4 .0 9 6mbit/s -- x
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 11 8 2000-07 figure 37 system interface (t1/j1) receive elastic buffer receive jitter attenuator receive backplane transmit backplane receive data transmit data receive clock transmit clock s y nc2 rcl k plb b y p b y p transmit jitter attenuator scl k r scl kx rsigm s y pr rfm rmfb dlr/rsig rdo x sig x sigm x mfb dl x x di x mfs s y p x system clocks transmit elastic buffer s y nc b y p f0050
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 11 9 2000-07 figure 38 receive system interface clocking (t1/j1) itd10949 ~ ~ ~ ~ frame 1 frame 2 frame 3 frame 11 frame 12 frame 1 frame 2 ~ ~ ~ ~ bit 255 bit 0 bit 255 t 4 mbit interface 2 mbit interface programmable via rc0/1 rdo rmfb sypr sypr sclkr 8.192 mhz 1.544 mhz sclkr 2 mbit/s data rate rdo/rsig rdo/rsig (sclkr = 8.192 mhz) 4 mbit/s data rate rfm receive frame marker rsigm time-slot marker rtr1...4 4 mbit/s data rate (sclkr = 8.192 mhz) rdo/rsig bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 (sclkr = 1.544 mhz) rdo bit 192 fdl bit 1 bit 2 bit 3 bit 4 programmable via rc0/1 t dlr dl bit marker 1.544 mbit interface 1.544 mbit/s data rate 4 mbit interface 2 mbit interface (e.g. f12 frame format) sample edge edge trigger ts0 sample edge marks any bit position marks any time-slot 1) only falling trigger edge shown, depending on bit sic3.resr 1) rco/1
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 120 2000-07 figure 39 2.048 mbit/s receive signaling highway (t1/j1) figure 40 1.544 mbit/s receive signaling highway (t1/j1) itt10519 f01234567 d c b a abcd d c b a ts0 ts1 ts4 ts31 t sypr sclkr rdo rsig t = time-slot offset = fs/dl-bit f = signaling bits for time-slot 1-24 abcd ts2 ts3 01 7 6 5 4 3 2 01 7 6 5 4 3 2012 7 6 5 4 3 fs/dl-channel idle-channel time-slot mapping acc. channel translation mode 0 f abcd itt10521 0123456701234567 01234567 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ d c b a abcd d c b a ts0 ts1 ts23 125 s t sypr sclkr rdo rsig t = time-slot offset = fs/dl-bit f = signaling bits for time-slot 1-24 abcd ~ ~ f f f c b ad f
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 121 2000-07 5.2.1 time slot assigner (t1/j1) the falc ? -lh offers the flexibility to c onnect data during certain time slots, as defined by registers rtr1- 4 and ttr1- 4 , to the rfifo and x fifo, respectively. any combinations of time slots can be programmed for the receive and transmit directions. if ccr1.eits = 1 the selected time slots (rtr1- 4 ) are stored in the rfifo of the signaling controller and the x fifo contents is inserted into the transmit path as controlled by registers ttr1- 4 . in receive direction, transparency for ternary or dual/single rail unipolar data is always achieved if the receiver is in the synchronous state and bit fmr5.rtf is set. all bits in the f-bit position of the incoming multiframe are forwarded to rdo and inserted in the fs/dl time-slot or in the f-bit position. in asynchronous state the received data may be transparently switched through if bit fmr2.dais is set. for the receive path bit fmr5.rtf has the same function as bit fmr 4 .tm. table 28 time slot assigner (t1/j1) receive time slot register transmit time slot register time slots receive time slot register transmit time slot register time slots rtr 1.7 ttr 1.7 0 rtr 3.7 ttr 3.7 16 rtr 1.6 ttr 1.6 1 rtr 3.6 ttr 3.6 17 rtr 1.5 ttr 1.5 2 rtr 3.5 ttr 3.5 1 8 rtr 1. 4 ttr 1. 4 3rtr3. 4 ttr 3. 4 1 9 rtr 1.3 ttr 1.3 4 rtr 3.3 ttr 3.3 20 rtr 1.2 ttr 1.2 5 rtr 3.2 ttr 3.2 21 rtr 1.1 ttr 1.1 6 rtr 3.1 ttr 3.1 22 rtr 1.0 ttr 1.0 7 rtr 3.0 ttr 3.0 23 rtr 2.7 ttr 2.7 8 rtr 4 .7 ttr 4 .7 2 4 rtr 2.6 ttr 2.6 9 rtr 4 .6 ttr 4 .6 25 rtr 2.5 ttr 2.5 10 rtr 4 .5 ttr 4 .5 26 rtr 2. 4 ttr 2. 4 11 rtr 4 . 4 ttr 4 . 4 27 rtr 2.3 ttr 2.3 12 rtr 4 .3 ttr 4 .3 2 8 rtr 2.2 ttr 2.2 13 rtr 4 .2 ttr 4 .2 2 9 rtr 2.1 ttr 2.1 1 4 rtr 4 .1 ttr 4 .1 30 rtr 2.0 ttr 2.0 15 rtr 4 .0 ttr 4 .0 31
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 122 2000-07 figure 41 receive fs/dl bits in time slot 0 on rdo (t1/j1) itd06460 12345678 fs/dl time-slot msb lsb fs/dl data bit fs/dl
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 123 2000-07 5.3 transmit path in t1/j1 mode compared to the receive paths the inverse functions are performed for the transmit direction. the interface to the transmit system highway is realized by two data buses, one for the data x di and one for the signaling data x sig. the time slot assignment is equivalent to the receive direction. all unequipped (idle) time slots are ignored. latching of data is controlled by the system clock (scl kx ) and the synchronous pulse (s y p x / x mfs) in conjunction with the programmed offset values for the transmit time slot/clock slot counters x c1/0. the frequency of the working clock for the transmit system interface is programmable by sic1.s x sc. refer also to table 27 on page 117 . the received bit stream on ports x di and x sig can be multiplexed internally on a time slot basis, if enabled by sic3.ttrf = 1, if not serial cas mode is selected (see chapter 5.1.12.2 on page 115 ). the data received on port x sig can be sampled if the transmit signaling marker x sigm is active high. data on port x di is sampled if x sigm is low for the respective time slot. programming the x sigm marker is done with registers ttr1- 4 .
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 12 4 2000-07 figure 42 transmit system interface clocking: 1.544 mhz (t1/j1) frame1 frame2 frame3 frame12 frame1 frame2 frame3 x di x mfb x mfs s y p x trigger edge bit 0 sample edge scl kx x di fdl bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 dl x dl bit marker 1) delay t is programmable by x c0/1 ; s y p x t 1) x sigm time slot marker f00 30
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 125 2000-07 figure 43 transmit system interface clocking: 8 mhz/4 mbit/s (t1/j1) frame1 frame2 frame3 frame12 frame1 frame2 frame3 x di x mfs s y p x trigger edge bit 0 sample edge scl kx x di/ x sig rc0.sics = 0 dl x dl-bit marker rc0.sics = 0 1) delay t is programmable by x c0/1 ; s y p x t 1) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 dl x dl-bit marker rc0.sics = 1 x di/ x sig rc0.sics = 1 x sigm time-slot marker x tr1... 4 rc0.sics = 0(1) blatt-1
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 126 2000-07 figure 44 2.048 mbit/s transmit signaling clocking (t1/j1) figure 45 1.544 mbit/s transmit signaling highway (t1/j1) itt10520 f01234567 d c b a abcd d c b a ts0 ts1 ts4 ts31 t sypx sclkx xdi xsig t = time-slot offset = fs/dl-bit f = signaling bits for time-slot 1-24 abcd ts2 ts3 01 7 6 5 4 3 2 01 7 6 5 4 3 2012 7 6 5 4 3 fs/dl-channel idle-channel time-slot mapping acc. channel translation mode 0 f abcd itt10522 0123456701234567 01234567 ~ ~ ~ ~ ~ ~ ~ ~ ~ d c b a abcd d c b a ts0 ts1 ts23 125 s t sypx sclkx xdi xsig t = time-slot offset = fs/dl-bit f = signaling bits for time-slot 1-24 abcd ~ ~ f f f c b ad f ~
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 127 2000-07 figure 46 signaling marker for cas/cas-cc applications (t1/j1) itd06462 frame 1 frame 2 frame 3 frame 12 multiframe n (e.g. f12) 24 1 2 3 6 5 4 7 8 9 19 20 21 22 23 24 fs/ dl dl fs/ signals in channel translation mode 0 signals in channel translation mode 1 fs/ dl dl fs/ 1 18 17 16 2 1 19 20 21 22 23 24 rd0 xdi xmfb rmfb xdi rd0 xdi rd0 ~ ~ ~ ~ ~ ~~ ~ ~ ~ 1) xsigm rsigm xsigm rsigm rsigm and xsigm are programed via registers rtr1 channel 24 1) 4 to mark only ... 4 / ttr1 ... 1)
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 12 8 2000-07 figure 47 signaling marker for cas-br applications (t1/j1) itd06463 frame 1 frame 2 frame 6 frame 12 multiframe n (e.g.f12) 24 1 2 3 6 5 4 7 8 9 19 20 21 22 23 24 fs/ dl dl fs/ signals in channel translation mode 0 signals in channel translation mode 1 fs/ dl dl fs/ 1 18 17 16 2 1 19 20 21 22 23 24 rd0 xdi xmfb rmfb xdi rd0 xsigm rsigm xdi rd0 xsigm rsigm signals in frames 6 and 12 of each multiframe signals in frames 6 and 12 of each multiframe rsigm and xsigm will mark the robbed bit positions if xco.brm is set high 1) ~ ~~ ~ ~ ~ ~ ~~ ~ ~ ~~ ~ ~ ~~ ~ 1) 1)
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 12 9 2000-07 transmit direction fs/dl data on system transmit highway ( x di), time slot 0. figure 48 transmit fs/dl bits on x di (t1/j1) 5.3.1 transmit signaling controller (t1/j1) similar to the receive signaling controller the same signaling methods and the same time slot assignment are provided. the falc ? -lh performs the following signaling and data link methods. 5.3.1.1 hdlc or lapd access the transmit signaling controller of the falc ? -lh performs the flag generation, crc generation, zero bit-stuffing and programmable idle code generation. buffering of transmit data is done in the 6 4 byte deep x fifo. the signaling information is multiplexed internally with the data applied on port x di or x sig. in signaling controller transparent mode, fully transparent data transmission without hdlc framing is performed. optionally the falc ? -lh supports the continuous transmission of the x fifo contents. operating in hdlc or bom mode ?flags? or ?idle? may be transmitted as interframe timefill. the falc ? -lh offers the flexibility to insert data during certain time slots. any combinations of time slots may be programmed separately for the receive and transmit directions. 5.3.1.2 cas bit-robbing (t1/j1) the signaling controller inserts the bit stream either on the transmit line side or if external signaling is enabled on the transmit system side. signaling data may be sourced internally from registers x s1-12 or externally on port x sig. in external signaling mode the signaling data is sampled with the working clock of the transmit system interface (scl kx ) in conjunction with the transmit synchronous pulse (s y p x ). data on x sig is latched in the bit positions 5- 8 per time slot, bits 1- 4 are itd06460 12345678 fs/dl time-slot msb lsb fs/dl data bit fs/dl
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 130 2000-07 ignored. the fs/dl bit is sampled on port x sig and inserted in the outgoing data stream. the received cas multiframe is inserted frame aligned into the data stream on x di. data sourced by the internal signaling controller overwrites the external signaling data. internal multiplexing of data and signaling data may be disabled on a per time slot basis (clear channel capability). this is also valid when using the internal and external signaling mode. 5.3.1.3 data link access in esf/f24 and f72 format (t1/j1) the dl-channel protocol is supported as follows: - access is done on a multiframe basis via registers x dl1-3 or - hdlc access or transparent transmission (non hdlc mode) from x fifo the signaling information stored in the x fifo is inserted in the dl bits of frame 26 to 72 in f72 format or in every other frame in esf format. operating in hdlc or bom mode ?flags? or ?idle? may be transmitted as interframe timefill.
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 131 2000-07 5.3.2 transmit elastic buffer (t1/j1) thetransmitelasticstorewithasizeofmax.2 1 9 3 bit (two frames) serves as a temporary store for the pcm data to adapt the system clock (scl kx ) to the internally generated clock for the transmit data, and to re-translate time slot structure used in the system to that of the line side. its optimal start position is initiated when programming the transmit time slot offset values. a difference in the effective data rates of system side and transmit side may lead to an overflow/underflow of the transmit memory: thus, errors in data transmission to the remote end may occur. this error condition (transmit slip) is reported to the microprocessor via interrupt status registers. the received bit stream from pin x di is optionally stored in the transmit elastic buffer. the memory is organized as the receive elastic buffer. programming of the transmit buffer size is done by sic1. x bs1/0 : x bs1/0 = 00 : bypass of the transmit elastic buffer x bs1/0 = 01 : one frame buffer or 1 9 3bits maximum of wander amplitude (peak-to-peak): (1 u i = 6 48 ns ) system interface clocking rate: 8 .1 9 2mhz: max. wander : 8 0 u i in channel translation mode 0 max. wander : 50 u i in channel translation mode 1 system interface clocking rate: 1.5 44 mhz: max. wander: 7 4u i average delay after performing a slip: 9 6bits x bs1/0 = 10 : two frame buffer or 3 8 6bits system interface clocking rate: 8 .1 9 2mhz: 1 4 2 u i in channel translation mode 0 7 8u i in channel translation mode 1 system interface clocking rate: 1.5 44 mhz: max. wander: 126 u i average delay after performing a slip: 1 9 3bits x bs1/0 = 11 : short buffer or 9 6bits: system interface clocking rate: 8 .1 9 2mhz: max. wander : 2 8u i in channel translation mode 0 ; channel translation mode 1 not supported system interface clocking rate: 1.5 44 mhz: max. wander: 3 8u i average delay after performing a slip: 48 bits the functions of the transmit buffer are: clock adaption between system clock (scl kx ) and internally generated transmit route clock ( x cl k ). compensation of input wander and jitter. frame alignment between system frame and transmit route frame
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 132 2000-07 reporting and controlling of slips writing of received data from x di is controlled by scl kx and s y p x / x mfs in conjunction with the programmed offset values for the transmit time slot/clock slot counters. reading of stored data is controlled by the clock generated by dco- x circuitry and the transmit framer. with the dejittered clock data is read from the transmit elastic buffer and are forwarded to the transmitter. reporting and controlling of slips is automatically done according to the receive direction. positive/negative slips are reported in interrupt status bits isr5. x sp and isr5. x sn. a re-initialization of the transmit memory is done by re-programming the transmit time slot counter x c1 and with the next s y p x pulse. after that, this memory has its optimal start position. the frequency of the working clock for the transmit system interface is programmable by sic1.s x sc and sic1.srsc to be 1.5 44 or 8 .1 9 2mhz. generally the data or marker on the system interface are clocked off or latched on the falling edge of the scl kx clock. the following table gives an overview of the transmit buffer operating modes. table 29 transmit buffer operating modes (t1/j1) sic1. x bs1...0 buffer size ts offset programming slip performance 00 scl kx= 1.5 44 mhz bypass enabled no 00 scl kx=8 .1 9 2mhz 1 frame enabled yes 1) 1) compatible with falc ? 5 4 01 short buffer enabled yes 10 1 frame enabled yes 11 2 frames enabled yes if x sw. x tm = 1, slip is performed on the frame boundary
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 133 2000-07 5.3.3 transmitter (t1/j1) the serial bit stream is then processed by the transmitter which has the following functions: frame/multiframe synthesis of one of the four selectable framing formats insertion of service and data link information ais generation (blue alarm) remote alarm (yellow alarm) generation crc generation and insertion of crc bits crc bits inversion in case of a previously received crc error or in case of activating per control bit generation of loop u p/down code idle code generation per ds0 the frame/multiframe boundaries of the transmitter may be externally synchronized by using the s y p x / x mfs pin. any change of the transmit time slot assignment subsequently produces a change of the framing bit positions on the line side. this feature is required if signaling and data link bits are routed through the switching network and are inserted in transmit direction via the system interface. in loop-timed configuration (lim2.elt = 1) disconnecting the control of the transmit system highway from the transmitter is done by setting fmr5. x tm. the transmitter is now in a free running mode without any possibility to update the multiframe position in case of changing the transmit time slot assignment. the fs/dl bits are generated independently of the transmit system interface. for proper operation the transmit elastic buffer size must be programmed to 2 frames. the contents of selectable time slots may be overwritten by the pattern defined via register idle. the selection of ?idle channels? is done by programming the three-byte registers icb1 ? icb3. if ami coding with zero code suppression (b7-stuffing) is selected, ?clear channels? without b7-stuffing can be defined by programming registers ccb1 ? ccb3.
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 13 4 2000-07 5.3.4 transmit line interface (t1/j1) the analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar) return to zero signals of the appropriate programmable shape. the unipolar data is provided by pin x di and the digital transmitter. similar to the receive line interface three different data types are supported: figure 49 transmitter configuration (t1/j1) ternary signal single rail data is converted into a ternary signal which is output on pins x l1 and x l2. selection between b 8z s or simple ami coding with zero code suppression (b7 stuffing) is provided. b7 stuffing may be disabled on a per time slot basis (clear channel capability). selected by fmr0. x c1/0 and lim1.drs = 0. dual rail data pcm( + ), pcm(-) at multifunction ports x dop and x don with 50 % or 100 % duty cycle and with programmable polarity. line coding is done in the same way as in the ternary interface. selected by fmr0. x c1 = 1 and lim1.drs = 1. u nipolar data on port x oidistransmittedinnr z (non return to z ero) with 100 % duty cycle to a fibre optical interface. clocking off data is done with the rising edge of the transmit clock x cl k (15 44 khz) and with a programmable polarity. selection is done by fmr0. x c1...0 = 00 and lim1.drs = 1. table 30 example transmitter configuration values (t1/j1) parameter t1 j1 characteristic impedance [ ? ] 100 110 r 1 ( 1 % ) [ ? ] 55 t2 : t1 1 : 1 : its10968 line t 1 t 2 xl2 xl1 r 1 1 r falc r 2 2
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 135 2000-07 5.3.5 programmable pulse shaper and line build-out (t1/j1) in long haul applications the transmit pulse masks are optionally generated according to fcc6 8 and ansi t1. 4 03. to reduce the crosstalk on the received signals the falc ? -lh offers the ability to place a transmit attenuator in the data path. transmit attenuation is selectable from 0, -7.5, -15 or -22.5 db (register lim2.lbo2/1). ansi t1. 4 03 defines only 0...-15 db. the falc ? -lh includes a programmable pulse shaper to satisfy the requirements of ansi t1. 102, also various ds1, ds x -1 specifications are met. the amplitude of the pulse shaper is programmable individually via the microprocessor interface to allow a maximum of different pulse templates. the line length is selected by programming the registers x pm2...0 as shown for typical values in the table below. the values with transformer ratio: 1: ; cable: p u lp 22awg (100 ? ) ; serial resistors: 5 ? .the x pm register values are given in decimal. the transmitter requires an external step up transformer to drive the line. the required programming values might vary between applications and have to be optimized according to external component values, parasitics, and so on. table 31 pulse shaper programming (t1/j1) range in m range in ft. x pm0 x pm1 x pm2 x p04- x p00 x p14- x p10 x p24- x p20 x p34- x p30 hexadecimal decimal 0... 4 0 0...133 1 99 b01252 4 63 4 0... 8 1 133...266 5b 9 f0127267 3 8 1...122 266...3 99 7d ab 01 2 9 27 10 3 122...162 3 99 ...533 7f b7 01 31 27 13 3 162...200 533...655 5f bb 01 31 26 1 4 3 2
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 136 2000-07 5.3.6 transmit line monitor (t1/j1) the transmit line monitor compares the transmit line pulses on x l1 and x l2 with the transmit input signals received on pins x l1m and x l2m. the monitor detects faults on the primary side of the transformer and protects the device from damage by setting the transmit lines into high impedance state automatically. faults on the secondary side can not be detected. to detect shorts, the configuration shown in figure 50 must be provided and the default (reset) value of registers x pm0...2 must be selected. otherwise a short detection can not be guaranteed. two conditions are detected by the monitor: ?transmit line ones density? (more than 31 consecutive zeroes) and ?transmit line shorted?. in both cases a transmit line monitor status change interrupt is provided. figure 50 transmit line monitor configuration (t1/j1) its09746 pulse shaper monitor line tri xpm2.daxlt/xlt xdata xl1 xl2 xl2m xl1m r falc -lh
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 137 2000-07 5.4 framer operating modes (t1/j1) 5.4.1 general activatedwithbitfmr1.pmod = 1. pcm line bit rate : 1.5 44 mbit/s single frame length : 1 9 3bit,no.1?1 9 3 framing frequency : 8 khz organization : 2 4 time slots, no. 1 ? 2 4 with 8 bits each, no. 1 ? 8 and one preceding f bit selection of one of the four permissible framing formats is performed by bits fmr 4 .fm1...0. these formats are: f4 : 4 -frame multiframe f12 : 12-frame multiframe (d 4 ) esf : extended superframe (f2 4 ) f72 : 72-frame multiframe (slc 9 6) the operating mode of the falc ? -lh is selected by programming the carrier data rate and characteristics, line code, multiframe structure, and signaling scheme. the falc ? -lh implements all of the standard and/or common framing structures pcm 2 4 (t1, 1.5 44 mbit/s) carriers. the internal hdlc-controller supports all signaling procedures including signaling frame synchronization/synthesis in all framing formats. after reset, the falc ? -lh must be programmed with fmr1.pmod = 1 to enable the t1(pcm2 4 ) mode. switching between the framing formats is done via bit fmr 4 .fm1/0 for the receiver and for the transmitter. 5.4.2 general aspects of synchronization synchronization status is reported via bit frs0.lfa (loss of frame alignment). framing errors (pulse frame and multiframe) are counted by the framing error counter fec. loss of frame alignment (frs0.lfa or opt. frs0.lmfa) is declared if: 2 out of 4 framing bits or 2 out of 5 framing bits or 2 out of 6 framing bits in f 4 /12/72 format or 2 out of 6 framing bits per multiframe period in esf format or 4 consecutive multiframe pattern in esf format are incorrect. it depends on the selected multiframe format and optionally on bit fmr2.ssp which framing bits are observed: f 4 :ft bits frs0.lfa f12, f72:ssp = 0: ft bits frs0.lfa: fs bits frs0.lfa
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 13 8 2000-07 and frs0.lmfa ssp = 1:ft frs0.lfa fs frs0.lmfa esf:esf framing bits frs0.lfa the resynchronization procedure may be controlled by either one of the following procedure: automatically (fmr 4 .a u to = 1). additionally, it may be triggered by the user by setting/resetting one of the bits fmr0.frs (force resynchronization) or fmr0.e x ls (external loss of frame). u ser controlled, exclusively, via above control bits in the non-auto-mode (fmr 4 .a u to = 0). ft and fs bit conditions, i.e. pulse frame alignment and multiframe alignment can be handled separately if programmed via bit fmr2.ssp. thus, a multiframe re- synchronization can be automatically initiated after detecting 2 errors out of 4 /5/6 consecutive multiframing bits without influencing the state of the terminal framing. in the synchronous state, the setting of fmr0.frs or fmr0.e x ls resets the synchronizer and initiates a new frame search. the synchronous state is reached if there is only one definite framing candidate. in the case of repeated apparent simulated candidates, the synchronizer remains in the asynchronous state. in asynchronous state, the function of fmr0.e x ls is the same as above. setting bit fmr0.frs induces the synchronizer to lock onto the next available framing candidate if there is one. otherwise, a new frame search is started. this is useful in case the framing pattern that defines the pulseframe position is imitated periodically by a pattern in one of the speech/data channels. the control bit fmr0.e x ls should be used first because it starts the synchronizer to search for a definite framing candidate. to observe actions of the synchronizer, the frame search restart flag frs0.fsrf is implemented. it toggles at the start of a new frame search if no candidate has been found at previous attempt. when resynchronization is initiated, the following values apply for the time required to achieve the synchronous state in case there is one definite framing candidate within the data stream: table 32 resynchronization timing (t1/j1) frame mode average maximum units f 4 f12 esf f72 1.0 3.5 3. 4 13.0 1.5 4 .5 6.125 17.75 ms ms ms ms
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 13 9 2000-07 figure 51 influences on synchronization status (t1/j1) itd03574 auto-mode definite candidate synchronous asynchronous exls frs don doff synchronous asynchronous non-auto-mode definite candidate exls, frs don doff exls, frs synchronous multiple candidates asynchronous multiple candidates synchronous asynchronous exls, frs frs don doff exls frs 1) exls, frs frs don doff exls frs 1) : depends on the disturbance d one disturbance :
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 1 4 0 2000-07 figure 51 gives an overview of influences on synchronization status for the case of different external actions. activation of auto-mode and non-auto mode is performed via bit fmr 4 .a u to. generally, for initiating resynchronization it is recommended to use bit: fmr0.e x ls first. in case where the synchronizer remains in the asynchronous state, bit fmr0.frs may be used to enforce it to lock onto the next framing candidate, although it might be a simulated one. 5.4.3 4-frame multiframe (f4 format, t1/j1) the allocation of the ft bits (bit 1 of frames 1 and 3) for frame alignment signal is shown in table 33 . remote alarm (yellow alarm) is indicated by setting bit 2 to ?0? in each time slot. 5.4.3.1 synchronization procedure for multiframe synchronization, the terminal framing bits (ft bits) are observed. the synchronous state is reached if at least one terminal framing candidate is definitely found, or the synchronizer is forced to lock onto the next available candidate (fmr0.frs). 5.4.4 12-frame multiframe (d4 or sf format, t1/j1) normally, this kind of multiframe structure only makes sense when using the cas robbed bit signaling. the multiframe alignment signal is located at the fs-bit position of every other frame (refer to table 34 ). there are two possibilities of remote alarm (yellow alarm) indication: bit2 = 0 in each time slot of a frame, selected with bit fmr0.sraf = 0 the last bit of the multiframe alignment signal (bit 1 of frame 12) changes from ?0? to ?1?, selected with bit fmr0.sraf = 1. table 33 4-frame multiframe structure (t1/j1) frame number f t f s 1 2 3 4 1 ? 0 ? service bit service bit
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 1 4 1 2000-07 5.4.4.1 synchronization procedure in the synchronous state terminal framing (ft bits) and multiframing (fs bits) are observed, independently. further reaction on framing errors depends on the selected synchronization/resynchronization procedure (via bit fmr2.ssp): fmr2.ssp = ?0?: terminal frame and multiframe synchronization are combined. two errors within 4 /5/6 framing bits (via bits fmr 4 .ssc1/0) of one of the above leads to the asynchronous state for terminal framing and multiframing. additionally to the bit frs0.lfa, loss of multiframe alignment is reported via bit frs0.lmfa. the resynchronization procedure starts with synchronizing upon the terminal framing. if the pulse framing has been regained, the search for multiframe alignment is initiated. multiframe synchronization has been regained after two consecutive correct multiframe patterns have been received. fmr2.ssp = ?1?: terminal frame and multiframe synchronization are separated two errors within 4 /5/6 terminal framing bits lead to the same reaction as described above for the ?combined? mode. two errors within 4 /5/6 multiframing bits lead to the asynchronous state only for the multiframing. loss of multiframe alignment is reported via bit frs0.lmfa. the state of terminal framing is not influenced. now, the resynchronization procedure includes only the search for multiframe alignment. multiframe synchronization has been regained after two consecutive correct multiframe patterns have been received. table 34 12-frame multiframe structure (t1/j1) frame number f t f s signaling channel designation 1 2 3 4 5 6 7 8 9 10 11 12 1 ? 0 ? 1 ? 0 ? 1 ? 0 ? ? 0 ? 0 ? 1 ? 1 ? 1 ? 0/ra 1) 1) this bit can be used for remote alarm indication, if fmr0.sraf = 1 is set. in this case, this fs bit is not used to regain synchronization. a b
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 1 4 2 2000-07 5.4.5 extended superframe (f24 or esf format, t1/j1) the use of the first bit of each frame for the multiframe alignment word, the data link bits, and the crc bits is shown in table 35 on page 142 . 5.4.5.1 synchronization procedures for multiframe synchronization the fas bits are observed. synchronous state is reached if at least one framing candidate is definitely found, or the synchronizer is forced to lock onto the next available candidate (fmr0.frs). in the synchronous state the framing bits (fas bits) are observed. the following conditions selected by fmr 4 .ssc1/0 lead to the asynchronous state: two errors within 4 /5 framing bits table 35 extended superframe structure (f24, esf ; t1/j1) multiframe frame number f bits signaling channel designation multiframe bit number assignments fas dl crc 1 2 3 4 5 6 7 8 9 10 11 12 13 1 4 15 16 17 1 8 1 9 20 21 22 23 2 4 0 1 9 3 3 8 6 57 9 772 9 65 115 8 1351 15 44 1737 1 9 30 2123 2316 250 9 2702 2 89 5 30 88 3231 3 4 7 4 3667 3 8 60 4 053 4 2 4 6 44 3 9 ? ? ? 0 ? ? ? 0 ? ? ? 1 ? ? ? 0 ? ? ? 1 ? ? ? 1 m ? m ? m ? m ? m ? m ? m ? m ? m ? m ? m ? m ? ? e 1 ? ? ? e 2 ? ? ? e 3 ? ? ? e 4 ? ? ? e 5 ? ? ? e 6 ? ? a b c d
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 1 4 3 2000-07 two or more erroneous framing bits within one esf multiframe 4 incorrect (1 out of 6) consecutive multiframes independent of crc6 errors. there are four multiframe synchronization modes selectable via fmr2.mcsp and fmr2.ssp. fmr2.mcsp/ssp = 00 in the synchronous state, the setting of fmr0.frs or fmr0.e x ls resets the synchronizer and initiates a new frame search. the synchronous state is reached again, if there is only one definite framing candidate. in the case of repeated apparent simulated candidates, the synchronizer remains in the asynchronous state. in asynchronous state, setting bit fmr0.frs induces the synchronizer to lock onto the next available framing candidate if there is one. at the same time the internal framing pattern memory is cleared and other possible framing candidates are lost. fmr2.mcsp/ssp = 01 synchronization is achieved when 3 consecutive multiframe pattern are correctly found independent of the occurrence of crc6 errors. if only one or two consecutive multiframe pattern were detected the falc ? -lh stays in the asynchronous state, searching for a possible additionally available framing pattern. this procedure is repeated until the framer has found three consecutive multiframe pattern in a row. fmr2.mcsp/ssp = 10 this mode has been added in order to be able to choose multiple framing pattern candidates step by step. i.e. if in synchronous state the crc error counter indicates that the synchronization might have been based on an alias framing pattern, setting of fmr0.frs leads to synchronization on the next candidate available. however, only the previously assumed candidate is discarded in the internal framing pattern memory. the latter procedure can be repeated until the framer has locked on the right pattern (no extensive crc errors). the synchronizer is completely reset and initiates a new frame search, if there is no multiframing found. in this case bit fsr0.fsrf toggles. fmr2.mcsp/ssp = 11 synchronization including automatic crc6 checking synchronization is achieved when framing pattern are correctly found and the crc6 checksum is received without an error. if the crc6 check failed on the assumed framing pattern the falc ? -lh stays in the asynchronous state, searching for a possible available framing pattern. this procedure is repeated until the framer has locked on the right pattern. this automatic synchronization mode has been added in order to reduce the microprocessor load.
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 1 44 2000-07 5.4.5.2 remote alarm (yellow alarm) generation/detection remote alarm (yellow alarm) is indicated by the periodical pattern ?1111 1111 0000 0000 ?? in the dl bits. remote alarm is declared even in the presence of ber 1/1000. the alarm is reset when the ?yellow alarm pattern? no longer is detected. depending on bit rc1.sjr the falc ? -lh generates and detect the remote alarm accordingtojtg.70 4 . in the dl-bit position 16 continuos ?1? are transmitted if fmr0.sraf = 0andfmr 4 . x ra = 1. alternatively remote alarm can be indicated by setting bit 2 of every time slot after selecting fmr0.sraf = 1. 5.4.5.3 crc6 generation and checking (t1/j1) generation and checking of crc6 bits transmitted/received in the e1-e6 bit positions is done according to it u -t g.706. the crc6 checking algorithm is enabled via bit fmr1.crc. if not enabled, all check bits in the transmit direction are set. in the synchronous state received crc6 errors are accumulated in a 16 bit error counter and are additionally indicated by an interrupt status. crc6 inversion if enabled by bit rc0.crci, all crc bits of one outgoing extended multiframe are automatically inverted in case a crc error is flagged for the previous received multiframe. setting the bit rc0. x crci inverts the crc bits before transmitted to the distant end. this function is logically ored with rc0.crci. crc6 generation/checking according to jt g. 706 setting of rc1.sjr the falc ? -lh generates and check the crc6 bits according to jt g. 706. the crc6 checksum is calculated including the fs/dl bits. in synchronous state crc6 errors increment an error counter. 5.4.6 72-frame multiframe (slc96 format, t1/j1) the 72-multiframe is an alternate use of the fs-bit pattern and is used for carrying data link information. this is done by stealing some of redundant multiframing bits after the transmission of the 12-bit framing header (refer to figure 36 on page 146 ). the position of a and b signaling channels (robbed bit signaling) is defined by zero-to-one and one- to-zero transitions of the fs bits and is continued when the fs bits are replaced by the data link bits. remote alarm ( y ellowalarm)isindicatedbysettingbit2tozeroineachtimeslot.an additional use of the d bits for alarm indication is user defined and must be done externally.
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 1 4 5 2000-07 5.4.6.1 synchronization procedure in the synchronous state terminal framing (ft bits) and multiframing (fs bits of the framing header) are observed independently. further reaction on framing errors depends on the selected synchronization/resynchronization procedure (via bit fmr2.ssp): fmr2.ssp = ?0?: terminal frame and multiframe synchronization are combined two errors within 4 /5/6 framing bits (via bits fmr 4 .ssc1/0) of one of the above lead to the asynchronous state for terminal framing and multiframing. additionally to the resynchronization procedure starts with synchronizing upon the terminal framing. if the pulse framing has been regained, the search for multiframe alignment is initiated. multiframe synchronization has been regained after two consecutive correct multiframe patterns have been received. fmr2.ssp = ?1?: terminal frame and multiframe synchronization are separated two errors within 4 /5/6 terminal framing bits lead to the same reaction as described above for the ?combined? mode. two errors within 4 /5/6 multiframing bits lead to the asynchronous state only for the multiframing. loss of multiframe alignment is reported via bit frs0.lmfa. the state of terminal framing is not influenced. now, the resynchronization procedure includes only the search for multiframe alignment. multiframe synchronization has been regained after two consecutive correct multiframe patterns have been received.
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 1 4 6 2000-07 table 36 72-frame multiframe structure (t1/j1) frame number f t f s signaling channel designation 1 2 3 4 5 6 7 8 9 10 11 12 1 ? 0 ? 1 ? 0 ? 1 ? 0 ? ? 0 ? 0 ? 0 ? 1 ? 1 ? 1 b a 13 1 4 15 16 17 1 8 1 9 20 21 22 23 2 4 1 ? 0 ? 1 ? 0 ? 1 ? 0 ? ? 0 ? 0 ? 0 ? 1 ? 1 ? 1 b a 25 26 27 2 8 66 67 6 8 6 9 70 71 72 1 ? 1 ? 0 ? 1 ? 0 ? ? d ? d ? d ? d ? d b a
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 1 4 7 2000-07 5.4.7 summary of frame conditions (t1/j1) 1) in f12 (d 4 ) format bit 1 in frame 12 is excluded from the synchronization process, if fmr0.sraf = 1. table 37 summary frame recover/out of frame conditions (t1/j1) format frame recover condition out of frame condition f 4 only one ft pattern found, optional forcingonnextavailableftframing candidate 2 out of 4 /5/6 incorrect ft bits f12 (d 4 ) and f72 (slc 9 6) fmr2.ssp = 0: combined ft + fs framing search: first searching for ft pattern with optional forcing on next available framing candidates and then for 2 consecutive correct fs pattern 1) . fmr2.ssp = 1: separated ft + fs pattern search: loss of ft framing at first starts searching for ft and then for 2 consecutive correct fs pattern 1) . loss of fs framing starts only the fs pattern 1) .search. fmr2.ssp = 0:2outof 4 /5/6 incorrect ft or fs bits fmr2.ssp = 1: 2 out of 4 /5/6 incorrect ft bits search ft and fs framing bits, 2 out of 4 /5/6 incorrect fs bits search only the fs framing. f2 4 (esf) fmr2.mcsp/ssp = 00: only one fas pattern found, optional forcing on next available fas framing candidate with discarding of all remaining framing candidates. fmr2.mcsp/ssp = 01: 3 consecutive correct multiframing found independent of crc6 errors. fmr2.mcsp/ssp = 10: choosing multiple framing pattern step by step, optional forcing on next available fas framing pattern with discarding only of the previous assumed framing candidate. fmr2.mcsp/ssp = 11: fas framing correctly found and crc6 check error free. 2 out of 4 /5 incorrect fas bits or 2 out of 6 incorrect fas bits per multiframe or 4 consecutive incorrect multiframing pattern
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 1 48 2000-07 5.5 additional functions (t1/j1) 5.5.1 error performance monitoring and alarm handling alarm indication signal: detection and recovery is flagged by bit frs0.ais and isr2.ais. transmission is enabled via bit fmr1. x ais. loss of signal: detection and recovery is flagged by bit frs0.los and isr2.los. remote alarm indication: detection and release is flagged by bit frs0.rra and isr2.ra/rar. transmission is enabled via bit fmr 4 . x ra. excessive z eros: detection is flagged by bit frs1.e xz d. pulse density violation: detection is flagged by bit frs1.pden and isr0.pden. transmit line shorted: detection and release is flagged by bit frs1. x ls and isr1. x lsc. transmit ones density: detection and release is flagged by bit frs1. x lo and isr1. x lsc. table 38 summary of alarm detection and release (t1/j1) alarm detection condition clear condition red alarm or loss of signal (los) no transitions (logical zeros) in a programmable time interval of 16 to 4 0 9 6 consecutive pulse periods programmable receive input signal threshold programmable number of ones (1-256) in a programmable time interval of 16 to 4 0 9 6 consecutive pulse periods. a one is a signal with a level above the programmed threshold. or optionally the pulse density is fulfilled and no more than 15 or 99 contiguous zeros during the recovery interval are detected. blue alarm or alarm indication signal (ais) fmr 4 .ais3 = 0: less than 3 zeros in 12 frames or 2 4 frames (esf), fmr 4 .ais3 = 1: less than 4 zeros in 12 frames or less than 6 zeros in 2 4 frames (esf) active for at least one multiframe. fmr 4 .ais3 = 0: more than 2 zeros in 12 or 2 4 frames (esf), fmr 4 .ais3 = 1: more than 3 zeros in 12 frames or more than 5 zeros in 2 4 frames (esf)
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 1 49 2000-07 rra detection operates in the presence of 10 -3 bit error rate. y ellow alarm or remote alarm (rra) rc1.rram = 0: bit 2 = 0 in 255 consecutive time slots or fs bit = 1offrame12inf12(d 4 ) format or 8 x1, 8 x0 in the dl channel (esf ) rc1.rram = 1: bit 2 = 0ineverytimeslotper frame or fs bit = 1offrame12inf12(d 4 ) format or 8 x1, 8 x0 in the dl channel (esf ) rc1.rram = 0: set conditions no longer detected. rc1.rram = 1: bit 2 = 0 not detected in 3 consecutive frames or fs bit not detected in 3 consecutive multiframes or 8 x1, 8 x0 not detected for 3 times inarow(esf). excessive z eros (e xz d) more than 7 (b 8z s code) or more than 15 (ami code) contiguous zeros latched status: cleared on read pulse density violation (pden) less than 23 ones received in a floating time window of 1 9 2bits or more than 15 consecutive zeros (see chapter 5.5.9 ) transmit line short ( x ls) if x l1 and x l2 are shortened for at least 32 pulses ; pins x l1 and x l2 are forced into a high impedance state automatically, if bit x pm2.da x lt is reset. after 32 consecutive pulse periods the outputs x l1/2 are activated again and the internal transmit current limiter is checked. if a short between x l1/ 2 is still existing, the outputs x l1/ 2 are switched into high impedance state again. when the short disappears pins x l1/2 are activated automatically. transmit ones density ( x lo) 32 consecutive zeros in the transmit data stream on x l1/2 cleared with each transmitted pulse table 38 summary of alarm detection and release (t1/j1) (cont?d) alarm detection condition clear condition
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 150 2000-07 5.5.2 auto modes automatic remote alarm ( y ellow alarm) access if the receiver has lost its synchronization (frs0.lfa) a remote alarm (yellow alarm) can be sent to the distant end automatically, if enabled by bit fmr2.a x ra. in synchronous state the remote alarm bit is removed. automatic ais to system interface in asynchronous state the synchronizer enforces an ais to the receive system interface automatically. however, received data may be switched through transparently if bit fmr2.dais is set. automatic clock source switching in slave mode (lim0.mas = 0) the dco-r synchronizes to the recovered route clock. in case of loss of signal los the dco-r switches to master mode automatically. automatic freeze signaling: u pdating of the received signaling information is controlled by the freeze signaling status. optionally automatic freeze signaling can be disabled by setting bit sic3.daf. 5.5.3 error counter the falc ? -lh offers five error counters where each of them has a length of 16 bit. they record code violations, framing bit errors, crc6 bit errors, errored blocks and prbs bit errors. each of the error counters is buffered. u pdating the buffer is done in two modes: one second accumulation on demand via handshake with writing to the dec register in the one second mode an internal one second timer updates these buffers and reset the counter to accumulate the error events in the next one second period. the error counter can not overflow. error events occurring during reset are not lost. 5.5.4 errored second the falc ? -lh supports the error performance monitoring by detecting the following alarms or error events in the received data: framing errors, crc errors, code violations, loss of frame alignment, loss of signal, alarm indication signal, receive and transmit slips. with a programmable interrupt mask register imr 4 all these alarms or error events can generate an errored second interrupt (isr3.es) if enabled. 5.5.5 second timer additionally a one second timer interrupt is generated internally to indicate that the enabled alarm status bits or the error counters have to be checked. the timing is derived from rcl k .
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 151 2000-07 5.5.6 clear channel capability for support of common t1 applications, clear channels can be specified via the 3-byte register bank ccb1 ? ccb3. in this mode the contents of selected transmit time slots are not overwritten by internally or externally sourced bit-robbing and zero code suppression (b7 stuffing) information. remote alarm signaling, however, overwrites cleared channels. 5.5.7 in-band loop generation and detection the falc ? -lh generates and detects a framed or unframed in-band loop-up/activate (00001) and loop-down/deactivate (001) pattern according to ansi t1. 4 03 with bit error rates as high as 1/100. framed or unframed in-band loop code is selected by lcr1.fllb. replacing the in-band loop codes with transmit data is done by fmr5. x ld/ x l u . the falc ? -lh also offers the ability generating and detecting of a flexible in-band loop up - and down pattern (lcr1.llbp = 1). the loop up and loop down pattern is individual programmable from 2 to 8 bit in length (lcr1.lac1/0 and lcr1.ldc1/0). programming of loop codes is done in registers lcr2 and lcr3. status and interrupt-status bits inform the user whether a loop-up or loop-down code was detected. 5.5.8 transparent mode the transparent modes are useful for loopbacks or for routing data unchanged through the falc ? -lh. in receive direction, transparency for ternary or dual/single rail unipolar data is achieved if the receiver is in the synchronous state and fmr5.rtf has been selected. all bits in f-bit position of the incoming multiframe are forwarded to rdo and inserted in the fs/ dl time slot or in the f-bit position. in asynchronous state the received data may be transparently switched through if bit fmr2.dais is set. setting of bit loop.rtm disconnects control of the elastic buffer from the receiver. the elastic buffer is now in a ?free running? mode without any possibility to update the time slot assignment to a new frame position in case of re-synchronization of the receiver. together with fmr2.dais this function may be used to realize undisturbed transparent reception. setting bit fmr 4 .tm switches the falc ? -lh in transmit transparent mode: in transmit direction bit 8 of the fs/dl time slot from the system highway ( x di) is inserted in the f-bit position of the outgoing frame. for complete transparency the internal signaling controller, idle code generation, ais/ra alarm generation, single channel and payload loop back has to be disabled and ?clear channels? have to be defined via registers ccb1 3.
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 152 2000-07 5.5.9 pulse density detection the falc ? -lh examines the receive data stream on the pulse density requirement which is defined by ansi t1. 4 03. more than 15 consecutive zeros or less than 23 ones in each and every time window of 1 9 3 data bits are detected. violations of these rules are indicated by setting the status bit frs1.pden and the interrupt status bit isr0.pden. generation of the interrupt status may be programmed either with the detection or with any change of state of the pulse density alarm (gcr.sci). 5.6 test functions (t1/j1) 5.6.1 pseudo-random bit sequence generation and monitor the falc ? -lh has the ability to generate and monitor a 2 15 -1 and 2 20 -1 pseudo-random bit sequences (prbs). the generated prbs pattern is transmitted optionally inverted or not to the remote end via pins x l1/2 or x dop/n. generating and monitoring of prbs pattern is done according to it u -t o. 151 and tr62 4 11 with maximum 1 4 consecutive zero restriction. the prbs monitor senses the prbs pattern in the incoming data stream. synchronization is done on the inverted and non inverted prbs pattern. the current synchronization status is reported in status and interrupt status registers. enabled by bit lcr1.eprm each prbs bit error increments an error counter (bec). synchronization is reached within 4 00 ms with a probability of 99 . 9% and a ber of 1/10 (pattern defined by it u -t o.151).
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 153 2000-07 5.6.2 remote loop in the remote loopback mode the clock and data recovered from the line inputs rl1/2 or rdip/rdin are routed back to the line outputs x l1/2 or x dop/ x don via the analog or digital transmitter. as in normal mode they are also processed by the synchronizer and then sent to the system interface.the remote loopback mode is selected by setting the respective control bits lim1.rl + jatt. received data may be looped with or without the transmit jitter attenuator (fifo). figure 52 remote loop (t1/j1) its09750 rdo xdi rclk rl1 rl2 xl1 xl2 fifo xclk rclk dco1/2 framer rec. framer trans. store elast. elast. store recovery data clock + mux mux dco-r/dco- x
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 15 4 2000-07 5.6.3 payload loop back to perform an effective circuit test a line loop is implemented. if the payload loopback (fmr2.plb) is activated the received 1 9 2 bits of payload data is looped back to the transmit direction. the framing bits, crc6 and dl bits are not looped, if fmr 4 .tm = 0. they are originated by the falc ? -lh transmitter. if fmr 4 .tm = 1 the received fs/dl bit is sent transparently back to the line interface. following pins are ignored: x di, x sig, scl kx ,s y p x and x mfs. all the received data is processed normally. with bit fmr2.sais an ais can be sent to the system interface via pin rdo. figure 53 payload loop (t1/j1) note: returned data is not multiframe synchronous. its09748 clock + data rec. framer elast. store trans. framer rdo xdi rclk rl1 rl2 xl1 xl2 recovery sclkx sclkr mux ais-gen elast. store
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 155 2000-07 5.6.4 local loop the local loopback mode, selected by lim0.ll = 1, disconnects the receive lines rl1/2 or rdip/rdin from the receiver. instead of the signals coming from the line the data provided by system interface are routed through the analog receiver back to the system interface. the bit stream is transmitted on the line undisturbedly. however, an ais to the distant end can be enabled by setting fmr1. x ais without influencing the data looped back to the system interface. note that enabling the local loop usually invokes an out of frame error until the receiver can resynchronize to the new framing. the serial codes for transmitter and receiver have to be identical. in digital interface nr z mode, a clock must be provided on pin rcl k i( = rl2) to enable switching into local loop mode. figure 54 local loop (t1/j1) its09749 rdo xdi rclk ais-gen rl1 rl2 xl1 xl2 framer rec. framer trans. store elast. recovery data clock + mux elast. store
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 156 2000-07 5.6.5 single channel loop back (loopback of time slots) the channel loopback is selected via loop.eclb = 1. each of the 2 4 time slots may be selected for loopback from the system pcm input ( x di) to the system pcm output (rdo). this loopback is programmed for one time slot at a time selected by register loop. during loopback, an idle channel code programmed in register idle is transmitted to the remote end in the corresponding pcm route time slot. for the time slot test, sending sequences of test patterns like a 1 khz check signal should be avoided. otherwise, an increased occurrence of slips in the tested time slot disturbs testing. these slips do not influence the other time slots and the function of the receive memory. the usage of a quasi-static test pattern is recommended. figure 55 channel loopback (t1/j1) its09747 rdo xdi rclk rl1 rl2 xl1 xl2 idle code framer trans. framer rec. store elast. store elast. mux mux recovery data clock +
peb 2255 falc-lh v1.3 functional description t1/j1 data sheet 157 2000-07 5.6.6 alarm simulation (t1/j1) alarm simulation does not affect the normal operation of the device, i.e. all time slots remain available for transmission. however, possible ?real? alarm conditions are not reported to the processor or to the remote end when the device is in the alarm simulation mode. the alarm simulation is initiated by setting the bit fmr0.sim. the following alarms are simulated: loss of signal (red alarm) alarm indication signal ais (blue alarm) loss of pulse frame remote alarm (yellow alarm) indication receive and transmit slip indication framing error counter code violation counter crc6 error counter some of the above indications are only simulated if the falc ? -lh is configured in a mode where the alarm is applicable. the alarm simulation is controlled by the value of the alarm simulation counter: frs2.esc which is incremented by setting bit: fmr0.sim. clearing of alarm indications: automatically for los, remote (yellow) alarm, ais, and loss of synchronization or u ser controlled for slips by reading the corresponding interrupt status register isr3 or error counter have been cleared by reading the corresponding counter registers. clearing is only possible at defined counter steps of frs2.esc. for complete simulation (frs2.esc = 0), eight simulation steps are necessary.
peb 2255 falc-lh v1.3 operational description e1 data sheet 15 8 2000-07 6 operational description e1 6.1 operational overview e1 the falc ? -lh in principle can be operated in two modes, which are either e1 mode or t1/j1 mode. the device is programmable via a microprocessor interface which enables byte or word access to all control and status registers. after reset the falc ? -lh must be initialized first. general guidelines for initialization are described in sections ?device initialization in e1 mode? on page 158 and ?device initialization in t1/j1 mode? on page 163 the status registers are read-only and are updated continuously. normally, the processor reads the status registers periodically to analyze the alarm status and signaling data. 6.2 device reset e1 the falc ? -lh is forced to the reset state if a high signal is input on pin res for a minimum period of 20 s. during reset the falc ? -lh needs an active clocks on pins scl k r, scl kx , x tal1 and x tal3. all output stages except of cl k 16m, cl k 12m, cl k8 m, cl kx ,fsc , x cl k and rcl k are in a high impedance state, all internal flip- flops are reset and most of the control registers are initialized with default values. signals (for example rl1/2 receive line) should not be applied before the device is powered up. after reset the device is initialized to e1 operation. 6.3 device initialization in e1 mode after reset, the falc ? -lh is initialized for doubleframe format with register values listed in the following table. table 39 initial values after reset (e1) register reset value meaning fmr0 00 h nr z coding, no alarm simulation ;x l1/2 stay tristate fmr1 fmr2 00 h 00 h pcm 30 ? doubleframe format, 4 .0 9 6 mbit/s system data rate, no ais transmission to remote end, payload loop off. sic1 sic2 sic3 00 h 00 h 00 h 8 .1 9 2-mhz system clocking rate, receive buffer 2 frames, transmit buffer bypass, automatic freeze signaling
peb 2255 falc-lh v1.3 operational description e1 data sheet 15 9 2000-07 e1 initialization for a correct start up of the primary access interface a set of parameters specific to the system and hardware environment must be programmed after reset goes inactive. both the basic and the operational parameters must be programmed before the activation procedure of the pcm line starts. such procedures are specified in it u -t and etsi recommendations (e.g. fault conditions and consequent actions). setting optional parameters primarily makes sense when basic operation via the pcm line is guaranteed. table 40 gives an overview of the most important parameters in terms of signals and control bits which are to be programmed in one of the above steps. the sequence is recommended but not mandatory. accordingly, parameters for the basic and operational loop x sw x sp tswm 00 h 4 0 h 00 h 00 h channel loop back and single frame mode are disabled. all bits of the transmitted service word are cleared (bit 2 excluded). spare bit values are cleared. no transparent mode active. x c0 x c1 00 h 9 c h the transmit clock offset is cleared. thetransmittimeslotoffsetiscleared. rc0 rc1 00 h 9 c h the receive clock slot offset is cleared ; 1st channel phase is active on pcm highway. the receive time slot offset is cleared. idle icb 1 ? 4 00 h 00 h idle channel code is cleared. normal operation (no ?idle channel? selected). lim0 lim1 pcd pcr 00 h 00 h 00 h 00 h slave mode, local loop off, cl kx= 2.0 48 mhz active high, short haul mode, no los indication on rcl k analog interface selected, remote loop off pulse count for los detection cleared pulse count for los recovery cleared x pm2...0 7b h ,03 h ,00 h transmit pulse mask imr0... 4 ff h, ff h, ff h, ff h, ff h, all interrupts are disabled rtr1... 4 ttr1... 4 00 h, 00 h, 00 h, 00 h, no time slots selected mode pre 00 h 00 h signaling controller disabled preamble cleared rah1/2 ral1/2 fd h ,ff h ff h ,ff h compare register for receive address cleared table 39 initial values after reset (e1) (cont?d) register reset value meaning
peb 2255 falc-lh v1.3 operational description e1 data sheet 160 2000-07 set up, for example, may be programmed simultaneously. the bit fmr1.pmod should always be kept low (otherwise t1/j1 mode is selected). features like channel loop back, idle channel activation, extensions for signaling support, alarm simulation, ? may be activated later. transmission of alarms (e.g. ais, remote alarm) and control of synchronization in connection with consequent actions to remote end and internal system depend on the activation procedure selected. note: read access to unused register addresses: value should be ignored. write access to unused register addresses: should be avoided, or set to ? 00 ? hex. all control registers (except xfifo, xs1-16, cmdr, dec) are of type: read/ write. specific e1 register settings the following is a suggestion for a basic initialization to meet most of the e1 requirements. depending on different applications and requirement any other initialization can be used. table 40 initialization parameters (e1) basic set up e1 mode select specification of line interface and clock generation line interface coding loss of signal detection/recovery conditions system interface mode transmit offset counters receive offset counters ais to system interface fmr1.pmod = 0 lim0, lim1, x pm2...0 fmr0. x c1/0, fmr0.rc1/0 pcd, pcr, lim1, lim2 fmr1.imod x c0. x co, x c1. x to rc0.rco, rc1.rto fmr2.dais/sais operational set up e1 select framing framing additions synchronization mode signaling mode fmr2.rfs1/0, fmr1. x fs rc1.as y4 , rc1.swd fmr1.afr, fmr2.almf x sp, x sw, fmr1.ensa, x sa 8 ... 4 , tswm, mode, ccr1, ccr3, pre, rah1/2, ral1/2
peb 2255 falc-lh v1.3 operational description e1 data sheet 161 2000-07 e1 framer initialization the selection of the following modes during the basic initialization supports the etsi requirements for e-bit access, remote alarm and synchronization (please refer also to falc ? -lh driver code of the reference system eas y 2255-r1 and application notes) and helps to reduce the software load. they are very helpful especially to meet requirements as specified in ets300 011. table 41 line interface initialization (e1) register function fmr0. x c0 fmr0.rc0 lim1.drs fmr3.cmi the falc ? -lh supports requirements for the analog line interface as well as the digital line interface. for the analog line interface the codes ami and hdb3 are supported. for the digital line interface modes (dual or single rail) the falc ? -lh supports ami, hdb3, cmi (with and without hdb3 precoding) and nr z . pcd = 0a h los detection after 176 consecutive ?zeros? (fulfills g.775 spec). pcr = 15 h los recovery after 22 ?ones? in the pcd interval. (fulfills g.775). lim1.ril2-0 = 03 h los threshold (fulfills g.775 ; see dc characteristics) table 42 framer initialization (e1) register function x sp.a x s = 1 ets300 011 c 4 .x for instance requires the sending of e-bits in ts0 if crc 4 errors have been detected. by programming x sp.a x s = 1 the submultiframe status is inserted automatically in the next outgoing multiframe. x sp.ebp = 1 if the falc ? -lh has reached asynchronous state the e-bit is cleared if x sp.ebp = 0 and set if x sp.ebp = 1. ets300 011 requires that the e-bit is set in asynchronous state. fmr2.a x ra = 1 the transmission of rai via the line interface is done automatically by the falc ? -lh in case of loss of frame alignment (frs0.lfa = 1). if basic framing has been reinstalled rai is automatically reset. fmr2.frs1/2 = 10 fmr1.afr = 1 in this mode a search of double framing is automatically reinitiated if no crc 4 multiframing could be found within 8 ms. together with fmr2.a x ra = 1 this mode is essential to meet ets300 011 and reduces the processor load heavily.
peb 2255 falc-lh v1.3 operational description e1 data sheet 162 2000-07 note: after the device initialization a software reset should be executed by setting of bits cmdr.xres/rres. fmr2.almf = 1 the receiver initiates a new basic- and multiframing research if more than 9 1 4 crc 4 errors have been detected in one second. fmr2.frs1/0 = 11 in the interworking mode the falc ? -lh stays in double framing format if no multiframe pattern could be found in a time interval of 4 00 ms. this is also indicated by a 4 00 ms interrupt. additionally the extended interworking mode (fmr3.e x tiw = 1) will activate after 4 00 ms the remote alarm (fmr2.a x ra = 1) and will still search the multiframing without switching completely to the double framing. a complete resynchronization in an 8 ms interval is not initiated. table 43 hdlc controller initialization (e1) register function mode =88 h hdlc receiver active, no address comparison. ccr1 = 1 8 h enable signaling via ts0...31, interframe time fill with continuous flags. imr0.rme = 0 imr0.rpf = 0 imr1. x pr = 0 u nmask interrupts for hdlc processor requests. rtr3.ts16 = 1 ttr3.ts16 = 1 select ts16 for hdlc data reception and transmission. table 44 cas-cc initialization (e1) register function x sp.casen = 1 send cas info stored in the x s1...16 registers. imr0.casc = 0 enable interrupt with any data change in the rs1...16 registers. table 42 framer initialization (e1) (cont?d) register function
peb 2255 falc-lh v1.3 operational description t1/j1 data sheet 163 2000-07 7 operational description t1/j1 7.1 operational overview t1/j1 the falc ? -lh in principle can be operated in two modes, which are either e1 mode or t1/j1 mode. there are only minor differences between t1 and j1 mode which are described in table 48 . the device is programmable via a microprocessor interface which enables byte or word access to all control and status registers. after reset the falc ? -lh must be initialized first. general guidelines for initialization are described in sections ?device initialization in e1 mode? on page 158 and ?device initialization in t1/j1 mode? on page 163 the status registers are read-only and are updated continuously. normally, the processor reads the status registers periodically to analyze the alarm status and signaling data. 7.2 device reset t1/j1 the falc ? -lh is forced to the reset state if a high signal is input on pin res for a minimum period of 20 s. during reset the falc ? -lh needs an active clocks on pins scl k r, scl kx , x tal1 and x tal3. all output stages except of cl k 16m, cl k 12m, cl k8 m, cl kx ,fsc , x cl k and rcl k are in a high impedance state, all internal flip- flops are reset and most of the control registers are initialized with default values. signals (for example rl1/2 receive line) should not be applied before the device is powered up. after reset the device is initialized to e1 operation. switching to t1/j1 mode is done by software (fmr1.pmod = 1). 7.3 device initialization in t1/j1 mode after reset, the falc ? -lh is initialized for e1 doubleframe format. to initialize t1/j1 mode, bit fmr1.pmod has to be set high. after the internal clocking is settled to t1/ j1mode (takes up to 20 s), the following register values are initialized:
peb 2255 falc-lh v1.3 operational description t1/j1 data sheet 16 4 2000-07 . table 45 initial values after reset and fmr1.pmod = 1(t1/j1) register initiated value meaning fmr0 00 h nr z coding, no alarm simulation ;x l1/2 stay tristate fmr1 fmr2 10 h 00 h pcm 2 4 mode, 4 .0 9 6 mbit/s system data rate, no ais transmission to remote end or system interface, payload loop off, channel translation mode 0 sic1 sic2, sic3 00 h 00 h 00 h 8 .1 9 2-mhz system clocking rate, receive buffer 2 frames, transmit buffer bypass, automatic freeze signaling, data is active in the first channel phase loop 00 h channel loop back is disabled. fmr 4 fmr5 00 h 00 h remote alarm indication towards remote end disabled. lfa condition: 2 out of 4 framing bits, non-auto- synchronization mode, f12 multiframing, internal bit- robbing access disabled x c0 x c1 00 h 9 c h the transmit clock slot offset is cleared. the transmit time slot offset is cleared. rc0 rc1 00 h 9 c h the receive clock slot offset is cleared. the receive time slot offset is cleared. idle icb 1 3 00 h 00 h idle channel code is cleared. normal operation (no ?idle channels? selected). ccb 1 300 h normal operation (no clear channel operation). lim0 lim1 pcd pcr 00 h 00 h 00 h 00 h slave mode, local loop off, cl kx= 2.0 48 mhz active high, short haul mode, no los indication on rcl k analog interface selected, remote loop off pulse count for los detection cleared pulse count for los recovery cleared x pm2...0 7b h ,03 h ,00 h transmit pulse mask imr0- 4 ff h all interrupts are disabled rtr1- 4 ttr1- 4 00 h no time slots selected mode 00 h signaling controller disabled rah1/2 ral1/2 fd h ,ff h ff h ,ff h compare register for receive address cleared
peb 2255 falc-lh v1.3 operational description t1/j1 data sheet 165 2000-07 t1/j1 initialization for a correct start up of the primary access interface a set of parameters specific to the system and hardware environment must be programmed after pin res goes inactive (low). both the basic and the operational parameters must be programmed before the activation procedure of the pcm line starts. such procedures are specified in it u -t recommendations (e.g. fault conditions and consequent actions). setting optional parameters primarily makes sense when basic operation via the pcm line is guaranteed. table 46 gives an overview of the most important parameters in terms of signals and control bits which are to be programmed in one of the above steps. the sequence is recommended but not mandatory. accordingly, parameters for the basic and operational set up, for example, may be programmed simultaneously. the bit fmr1.pmod must always be kept high (otherwise e1 mode is selected). features like channel loop back, idle channel activation, clear channel activation, extensions for signaling support, alarm simulation, may be activated later. transmission of alarms (e.g. ais, remote alarm) and control of synchronization in connection with consequent actions to remote end and internal system depend on the activation procedure selected. table 46 initialization parameters (t1/j1) basic set up t1/j1 mode select specification of line interface and clock generation line interface coding loss of signal detection/recovery conditions system interface mode channel translation mode transmit offset counters receive offset counters ais to system interface fmr1.pmod = 1 lim0, lim1, x pm2-0 fmr0. x c1/0, fmr0.rc1/0 pcd, pcr, lim1, lim2 fmr1.imod fmr1.ctm x c0. x co, x c1. x to rc0.rco, rc1.rto fmr2.dais/sais operational set up t1/j1 select framing framing additions synchronization mode signaling mode fmr 4 .fm1/0 fmr1.crc, fmr0.sraf fmr 4 .a u to, fmr 4 .ssc1/0, fmr2.mcsp, fmr2.ssp fmr1.sigm, fmr5.eibr, x c0.brm, mode, ccr1, ccr3, rah1/2, ral1/2
peb 2255 falc-lh v1.3 operational description t1/j1 data sheet 166 2000-07 note: read access to unused register addresses: value should be ignored. write access to unused register addresses: should be avoided, or set to ? 00 ? hex. all control registers (except xfifo, xs1-12, cmdr, dec) are of type: read/write specific t1/j1 initialization the following is a suggestion for a basic initialization to meet most of the t1/j1 requirements. depending on different applications and requirements any other initialization can be used. table 47 line interface initialization (t1/j1) register function fmr0. x c0/1 fmr0.rc0/1 lim1.drs ccb1-3 the falc ? -lh supports requirements for the analog line interface as well as the digital line interface. for the analog line interface the codes ami (with bit 7stuffing) and b 8z s are supported. for the digital line interface modes (dual or single rail) the falc ? -lh supports ami (with bit 7 stuffing) and b 8z s. pcd = 0x0a los detection after 176 consecutive ?zeros? (fulfills g.775 spec, bellcore/at & t) pcr = 0x15 los recovery after 22 ?ones? in the pcd interval. (fulfills g.775, bellcore/at & t) lim1.ril2- 0 = 0x03 los threshold (fulfills g. 775, see dc characteristics). gcr.sci = 1 additional recovery interrupts. help to meet alarm activation and deactivation conditions in time. lim2.los2/1 = 01 automatic pulse density check on 15 consecutive zeros for los recovery condition (bellcore requirement) table 48 framer initialization (t1/j1) register function t1 j1 fmr 4 .ssc1/0 selection of framing sync conditions fmr 4 .fm1/0 select framing format fmr2.a x ra = 1 the transmission of rai via the line interface is done automatically by the falc ? -lh in case of loss of frame alignment (frs0.lfa = 1). if framing has been reinstalled rai is automatically reset
peb 2255 falc-lh v1.3 operational description t1/j1 data sheet 167 2000-07 rco.sjr 1) = 1 fmr0.sraf = 0 x sw. x ra = 1 remote alarm handling via dl- channel according to it u -t jg.70 4 using pattern ?1111111111111111? rco.sjr 1) = 0 crc6 calculation without fs/dl bits rco.sjr 1) = 1 crc6 calculation including fs/ dl bits fmr 4 .a u to = 1 automatic synchronization in case of definite framing candidate (frs0.fsrf). in case of multiple framing candidates and crc6 errors different resynchronization conditions can be programmed via fmr2.mcsp/ssp. fmr 4 .ssc1 = 1 fmr 4 .ssc0 = 1 fmr2.mcsp = 0 fmr2.ssp = 1 synchronization and resynchronization conditions, for details see register description. 1) remote alarm handling and crc6 calculation are commonly selected by bit rco.sjr table 49 initialization of the hdlc controller (t1/j1) register function mode =88 h hdlc receiver active, no address comparison ccr1 = 1 8 h enable signaling via time slot 0...31, interframe time fill with continuous flags imr0.rme = 0 imr0.rpf = 0 imr1. x pr = 0 select interrupts for hdlc processor requests rtr 4 .0 = 1 ttr 4 .0 = 1 select time slot 2 4 for hdlc data reception and transmission table 48 framer initialization (t1/j1) (cont?d) register function t1 j1
peb 2255 falc-lh v1.3 operational description t1/j1 data sheet 16 8 2000-07 note: after the device initialization a software reset should be executed by setting of bits cmdr.xres/rres. table 50 initialization of the cas-br controller (t1/j1) register function fmr5.eibr = 1 fmr1.sigm = 1 enable cas-br mode send cas-br information stored in x s1...12 imr1.case = 0 imr0.rsc = 0 enable interrupts which indicate the access to the x s1...12 cas- br registers and any data change in rs1...12
peb 2255 falc-lh v1.3 signaling controller operating modes data sheet 16 9 2000-07 8 signaling controller operating modes the hdlc controller can be programmed to operate in various modes, which are different in the treatment of the hdlc frame in receive direction. thus, the receive data flow and the address recognition features can be performed in a very flexible way, to satisfy almost any practical requirements. there are 4 different operating modes which can be set via the mode register. 8.1 hdlc mode all frames with valid addresses are forwarded directly via the rfifo to the system memory. depending on the selected address mode, the falc ? -lh can perform a 1 or 2 byte address recognition (mode.mds0). if a 2-byte address field is selected, the high address byte is compared with the fixed value feh or fch (group address) as well as with two individually programmable values in rah1 and rah2 registers. according to the isdn lapd protocol, bit 1 of the high byte address is interpreted as command/response bit (c/r) and is excluded from the address comparison to rah1. similarly, two compare values can be programmed in special registers (ral1, ral2) for the low address byte. a valid address is recognized in case the high and low byte of the address field correspond to one of the compare values. thus, the falc ? -lh can be called (addressed) with 6 different address combinations. hdlc frames with address fields that do not match any of the address combinations, are ignored by the falc ? -lh. in case of a 1-byte address, ral1 and ral2 are used as compare registers. the hdlc control field, data in the i-field and an additional status byte are temporarily stored in the rfifo. additional information can also be read from a special register (rsis). as defined by the hdlc protocol, the falc ? -lh performs the zero bit insertion/deletion (bit-stuffing) in the transmit/receive data stream automatically. that means, it is guaranteed that at least a ?0? will appear after 5 consecutive ?1?s. 8.1.1 non-auto-mode (mode.mds2...1 = 01) characteristics: address recognition, flag - and crc generation/check, bit-stuffing all frames with valid addresses are forwarded directly via the rfifo to the system memory. 8.1.2 transparent mode 1 (mode.mds2...0 = 101) characteristics: address recognition, flag - and crc generation/check, bit-stuffing only the high byte of a 2-byte address field is compared with registers rah1/2. the whole frame excluding the first address byte is stored in rfifo.
peb 2255 falc-lh v1.3 signaling controller operating modes data sheet 170 2000-07 8.1.3 transparent mode 0 (mode.mds2...0 = 100) characteristics: flag and crc generation/check, bit-stuffing no address recognition is performed and each frame is stored in the rfifo. 8.1.4 receive data flow the following figure gives an overview of the management of the received hdlc frames in the different operating modes. figure 56 hdlc receive data flow of falc ? -lh f0225 flag ctrl flag addr crc data rsis rsis rsis rsis rah1,2 ral1,2 2) 2) rah1,2 2) rah1,2 2) x 1) 1) 1) mode.mds(2:0) 0 1 1 non-auto/16 0 1 0 non-auto/ 8 1 0 1 transparent 1 1 0 0 transparent 0 description of symbols: compared with register stored in fifo or register 1) rfifo rfifo rfifo rfifo in case of 8 -bit address the control field starts here 1) crc is optionally stored in rfifo if ccr3.rcrc = 1 2) address is optionally stored in rfifo if ccr3.radd = 1
peb 2255 falc-lh v1.3 signaling controller operating modes data sheet 171 2000-07 8.1.5 transmit data flow the frames can be transmitted as shown below. figure 57 hdlc transmit data flow of falc ? -lh transmitting a hdlc frame via register cmdr. x hf, the address, the control fields and the data field have to be entered in the x fifo. if ccr3. x crc is set, the crc checksum will not be generated internally. the checksum has to be provided via the transmit fifo ( x fifo) as the last two bytes. the transmitted frame is closed automatically with a closing flag only. the falc ? -lh does not check whether the length of the frame, i.e. the number of bytes to be transmitted makes sense or not. 8.2 extended transparent mode characteristics: fully transparent in no hdlc mode, fully transparent data transmission/reception without hdlc framing is performed, i.e. without flag generation/recognition, crc generation/check, or bit- stuffing. this feature can be profitably used e.g. for: specific protocol variations transmission of a bom frame test purposes data transmission is always performed out of the x fifo. in transparent mode, the receive data is shifted into the rfifo. control (xhf) frame hdlc transmit address flag xfifo addr ctrl flag data checkram itd06456 crc
peb 2255 falc-lh v1.3 signaling controller operating modes data sheet 172 2000-07 8.3 signaling controller functions 8.3.1 shared flags the closing flag of a previously transmitted frame simultaneously becomes the opening flag of the following frame if there is one to be transmitted. the shared flag feature is enabled by setting bit sflg in control register ccr1. 8.3.2 preamble transmission if enabled via register ccr3, a programmable 8 -bit pattern (defined by register pre) is transmitted with a selectable number of repetitions after interframe timefill transmission is stopped and a new frame is ready to be sent. z ero bit insertion is disabled during preamble transmission. to guarantee correct function the programmed preamble value should be different to the receive address byte values. otherwise the preamble could be detected as valid address with shared flags. in bom mode the msb of the preamble should be reset in order to achieve a faster synchronization at the bom receiver. after the preamble has been sent, the transmitter inserts one sync byte (ff h ) automatically before sending the contents of the transmit fifo. 8.3.3 transparent transmission and reception when programmed in the extended transparent mode via the mode register (mds2...0 = 111), the falc ? -lh performs fully transparent data reception without hdlc framing, i.e. without flag deletion crc checking bit-stuffing in order to enable fully transparent data reception, bit mode.hrac has to be set and ff h has to be written to rah2. received data is always shifted into rfifo. data transmission is always performed out of x fifo by shifting the contents of x fifo directly into the outgoing data stream. transmission is initiated by setting cmdr. x tf. a sync byte ff h is automatically sent before the first byte of the x fifo is transmitted. 8.3.4 cyclic transmission (fully transparent) if the extended transparent mode is selected, the falc ? -lh supports the continuous transmission of the contents of the transmit fifo.
peb 2255 falc-lh v1.3 signaling controller operating modes data sheet 173 2000-07 after having written 1 to 32 bytes to x fifo, the command x rep and x tf via the cmdr register (bit 7 0 = ?00100100? = 2 4 h ) forces the falc ? -lh to transmit the data stored in x fifo repeatedly to the remote end. note: the cyclic transmission continues until a reset command (cmdr: sres) is issued or with resetting cmdr.xrep, after which continuous ? 1 ? s are transmitted. during cyclic transmission the xrep-bit has to be set with every write operation to cmdr. 8.3.5 crc on/off features as an option in hdlc mode the internal handling of received and transmitted crc checksum can be influenced via control bits ccr3.rcrc and ccr3. x crc. receivedirection the received crc checksum is always assumed to be in the 2 last bytes of a frame (crc-it u ), immediately preceding a closing flag. if ccr3.rcrc is set, the received crc checksum is written to rfifo where it precedes the frame status byte (contents of register rsis). the received crc checksum is additionally checked for correctness. if hdlc mode is selected, the limits for ?valid frame? check are modified (refer to description of bit rsis.vfr). transmit direction if ccr3. x crc is set, the crc checksum is not generated internally. the checksum has to be provided via the transmit fifo ( x fifo) as the last two bytes. the transmitted frame will only be closed automatically with a closing flag. the falc ? -lh does not check whether the length of the frame, i.e. the number of bytes to be transmitted makes sense or not. 8.3.6 receive address pushed to rfifo the address field of received frames can be pushed to the receive fifo (first one or two bytes of the frame). this function is useful with the extended address recognition. it is enabled by setting control bit ccr2.radd. 8.3.7 hdlc data transmission in transmit direction 2 32 byte fifo buffers are provided. after checking the x fifo status by polling bit sis. x fw or after an interrupt isr1. x pr (transmit pool ready), up to 32 bytes may be entered by the cp u to the x fifo. the transmission of a frame can be started by issuing an x hf command via the command register. if enabled, a specified number of preambles (defined by register pre) are sent optionally before transmission of the current frame starts. if the transmit command does not include an end of message indication (cmdr. x me), the falc ? -lh will repeatedly request for the next data block by means of an x pr interrupt as soon as
peb 2255 falc-lh v1.3 signaling controller operating modes data sheet 17 4 2000-07 no more than 32 bytes are stored in the x fifo, i.e. a 32-byte pool is accessible to the cp u . this process is repeated until the cp u indicates the end of message by x me command, after which frame transmission is finished correctly by appending the crc and closing flag sequence. consecutive frames may be share a flag, or may be transmitted as back- to-back frames, if service of x fifo is fast enough. in case no more data is available in the x fifo prior to the arrival of x me, the transmission of the frame is terminated with an abort sequence and the cp u is notified by interrupt isr1. x d u . the frame may be aborted by software using cmdr.sres. the data transmission sequence from the cp u ?s point of view is outlined in figure 58 . figure 58 interrupt driven data transmission (flow diagram) the activities at both serial and cp u interface during frame transmission (supposed frame length = 70 bytes) shown in figure 59 . itd08565 start transmit pool ready ? xpr interrupt, xfw bit in sis register or =1 write data (up to 32 to xfifo bytes) y message end of ? xtf/xhf command n y n command xtf/xhf end + xme
peb 2255 falc-lh v1.3 signaling controller operating modes data sheet 175 2000-07 figure 59 interrupt driven transmission example 8.3.8 hdlc data reception 2 32 byte fifo buffers are also provided in receive direction. there are different interrupt indications concerned with the reception of data: rpf (receive pool full) interrupt, indicating that a 32-byte block of data can be read from rfifo and the received message is not yet complete. rme (receive message end) interrupt, indicating that the reception of one message is completed. the following figure gives an example of a reception sequence, assuming that a ?long? frame (66 bytes) followed by two short frames (6 bytes each) are received. figure 60 interrupt driven reception sequence example itd10971 wr xfifo 32 bytes system interface interface cpu alls xpr xhf + xme 6 bytes wr xfifo xpr xpr xhf 32 bytes wr xfifo command xhf transmit frame (70 bytes) 32 32 6 r falc itd10972 rd rfifo 32 bytes rmc receive frame 1 (66 bytes) 32 6 rpf rpf 32 2 32 bytes rd rfifo rmc rme rd status rd2 bytes rme rmc rd6 bytes rd status rmc rme rmc rd status rd6 bytes 6 rf2 rf3 falc r interface cpu interface system
peb 2255 falc-lh v1.3 signaling controller operating modes data sheet 176 2000-07 8.3.9 s a bit access (e1) the falc ? -lh supports the s a bit signaling of time slot 0 of every other frame as follows: access via registers rsw/ x sw access via registers rsa 8 - 4 / x sa 4 - 8 capable of storing the information for a complete multiframe the access via the 6 4 byte deep receive/transmit fifo of the integrated signaling controller. this s a bit access gives the opportunity to transmit/receive a transparent bit stream as well as hdlc frames where the signaling controller automatically processes the hdlc protocol. enabling for receive direction is done by resetting of ccr1.eits = 0 and setting of registers x co.sa 4 e... 8 e as required. for transmit direction bits tswm.tsa 4 ... 8 have to be set as required, additionally. data written to the x fifo will subsequently transmit in the s a bit positions defined by register x c0.sa 8 e- 4 e and the corresponding bits of tswm.tsa 8 - 4 . any combination of s a bits can be selected. after the data has been sent out completely, ?all ones? or flags (ccr1.itf) are transmitted. the continuous transmission of a transparent bit stream, which is stored in the x fifo, can be enabled. with the setting of bit mode.hrac the received s a bits can be forwarded to the receive fifo. the access to and from the fifos is supported by isr0.rme/rpf and isr1. x pr/als. 8.3.10 bit oriented message mode (t1/j1) the falc ? -lh supports signaling and maintenance functions for t1/j1 - primary rate interfaces using the extended super frame format. the device supports the dl-channel protocol for esf format according to t1. 4 03-1 989 ansi or to at & ttr5 4 016 specification. the hdlc- and bit oriented message (bom) -receiver can be switched on/off independently. if the falc ? -lh is used for hdlc formats only, the bom receiver has to be switched off. if hdlc- and bom-receiver has been switched on (mode.hrac/brac), an automatic switching between hdlc and bom mode is enabled. storing of received dl bit information in the rfifo of the signaling controller and transmitting the x fifo contents in the dl bit positions is enabled by ccr1.edl x / eits = 10. after hardware (pin res = high) or software reset (cmdr.rres = 1) the falc ? -lh operates in hdlc mode. if eight or more consecutive ones are detected, the bom mode is entered. u pon detection of a flag in the data stream, the falc ? -lh switches back to hdlc-mode. operating in bom-mode, the falc ? -lh may receive an hdlc frame immediately, i.e. without any preceding flags. in bom-mode, the following byte format is assumed (the left most bit is received first). 111111110xxxxxx0 the falc ? -lh uses the ff h byte for synchronization, the next byte is stored in rfifo (first bit received: lsb) if it starts and ends with a ?0?. bytes starting and ending with a ?1? are not stored. if there are no 8 consecutive one?s detected within 32 bits, an interrupt isr0.isf is generated. however, byte sampling is not stopped.
peb 2255 falc-lh v1.3 signaling controller operating modes data sheet 177 2000-07 byte sampling in bom mode (t1/j1) a) b) two different bom reception modes can be programmed (by ccr1.brm). 10 byte packets: ccr1.brm = 0 after storing 10 bytes in rfifo the receive status byte marking a bom frame (rsis.hfr) is added as the eleventh byte and an interrupt (isr0.rme) is generated. the sampling of data bytes continues and interrupts are generated every 10 bytes until an hdlc flag is detected. continuous reception: ccr1.brm = 1 interrupts are generated every 32 (16, 4 , 2) bytes. after detecting an hdlc flag, byte sampling is stopped, the receive status byte is stored in rfifo and an rme interrupt is generated. the user may switch between these modes at any time. byte sampling may be stopped by deactivating the bom receiver (mode.brac). in this case the receive status byte is added, an interrupt is generated and hdlc-mode is entered. whether the falc ? -lh operates in hdlc or bom mode may be checked by reading the signaling status register (sis.bom). 1111 1111 1111 0011 0100 1111 1111 0011 0100 1110 1111 0011 0100 1101 1111 sync not stored new sync 1.byte stored 1.corrupted sync 2.byte stored 2.corrupted sync corrupted sync 1111 1111 0111 0110 1101 1111 0111 0110 1111 1111 0111 0110 0111 1111 sync 1.byte stored 1.corrupted sync 2.byte stored 2.sync 3.byte stored 3.corrupted sync
peb 2255 falc-lh v1.3 signaling controller operating modes data sheet 17 8 2000-07 8.3.10.1 data link access in esf/f72 format (t1/j1) the falc ? -lh supports the dl-channel protocol using the esf or f72 (slc 9 6) format as follows: sampling of dl bits is done on a multiframe basis and stored in the registers rdl1...3. a receive multiframe begin interrupt is provided to read the received data dl bits. the contents of registers x dl1...3 is subsequently sent out on the transmit multiframe basis if it is enabled via fmr1.edl. a transmit multiframe begin interrupt requests for writing new information to the dl-bit registers. if enabled by ccr1.edl x /eits = 10, the dl-bit information is stored in the receive fifo of the signaling controller. the dl-bits stored in the x fifoareinsertedintothe outgoing data stream. if ccr1.edl x is cleared, a hdlc- or a transparent- frame can be sent or received via the rfifo/ x fifo.
peb 2255 falc-lh v1.3 data sheet 17 9 2000-07 register description due to the different device function in e1 and t1/j1 mode, several registers and register bits have dedicated functions according to the selected operation mode. to maintain easy readability this chapter is divided into separate e1 and t1/j1 sections. please choose the correct description according to your application (e1 or t1/j1).
peb 2255 falc-lh v1.3 e1 registers data sheet 1 8 0 2000-07 9e1registers 9.1 e1 control register addresses table 51 e1 control register address arrangement address register type comment page 00 x fifo w transmit fifo 183 01 x fifo w transmit fifo 183 02 cmdr w command register 183 03 mode r/w mode register 185 0 4 rah1 r/w receive address high 1 185 05 rah2 r/w receive address high 2 186 06 ral1 r/w receive address low 1 186 07 ral2 r/w receive address low 2 186 0 8 ipc r/w interrupt port configuration 186 0 9 ccr1 r/w common configuration register 1 187 0a ccr3 r/w common configuration register 3 189 0b pre r/w preamble register 190 0c rtr1 r/w receive timeslot register 1 191 0d rtr2 r/w receive timeslot register 2 191 0e rtr3 r/w receive timeslot register 3 191 0f rtr 4 r/w receive timeslot register 4 191 10 ttr1 r/w transmit timeslot register 1 192 11 ttr2 r/w transmit timeslot register 2 192 12 ttr3 r/w transmit timeslot register 3 192 13 ttr 4 r/w transmit timeslot register 4 192 1 4 imr0 r/w interrupt mask register 0 193 15 imr1 r/w interrupt mask register 1 193 16 imr2 r/w interrupt mask register 2 193 17 imr3 r/w interrupt mask register 3 193 1 8 imr 4 r/w interrupt mask register 4 193 1 9 imr5 r/w interrupt mask register 5 193 1a fmr0 r/w framer mode register 0 193
peb 2255 falc-lh v1.3 e1 registers data sheet 1 8 1 2000-07 1b fmr1 r/w framer mode register 1 195 1c fmr2 r/w framer mode register 2 197 1d loop r/w channel loop back register 199 1e x sw r/w transmit service word 200 1f x sp r/w transmit spare bits 201 20 x c0 r/w transmit control 0 203 21 x c1 r/w transmit control 1 203 22 rc0 r/w receive control 0 204 23 rc1 r/w receive control 1 206 2 4x pm0 r/w transmit pulse mask 0 207 25 x pm1 r/w transmit pulse mask 1 207 26 x pm2 r/w transmit pulse mask 2 207 27 tswm r/w transparent service word mask 208 2 9 idle r/w idle channel code 209 2a x sa 4 r/w transmit sa 4 bit register 210 2b x sa5 r/w transmit sa5 bit register 210 2c x sa6 r/w transmit sa6 bit register 210 2d x sa7 r/w transmit sa7 bit register 210 2e x sa 8 r/w transmit sa 8 bit register 210 2f fmr3 r/w framer mode register 3 210 30 icb1 r/w idle channel register 1 212 31 icb2 r/w idle channel register 2 212 32 icb3 r/w idle channel register 3 212 33 icb 4 r/w idle channel register 4 212 3 4 lim0 r/w line interface mode 0 213 35 lim1 r/w line interface mode 1 214 36 pcd r/w pulse count detection 216 37 pcr r/w pulse count recovery 216 3 8 lim2 r/w line interface mode 2 217 3 9 lcr1 r/w loop code register 1 218 table 51 e1 control register address arrangement (cont?d) address register type comment page
peb 2255 falc-lh v1.3 e1 registers data sheet 1 8 2 2000-07 after ?reset? all control registers except the x fifo and x s1...16 are initialized to defined values. u nused bits have to be cleared (set to logical ?0?). 3a lcr2 r/w loop code register 2 220 3b lcr3 r/w loop code register 3 220 3c sic1 r/w system interface control 1 221 3d sic2 r/w system interface control 2 223 3e lim3 r/w line interface mode 3 224 4 0 sic3 r/w system interface control 3 224 60 dec w disable error counter 225 70 x s1 w transmit cas register 1 226 71 x s2 w transmit cas register 2 226 72 x s3 w transmit cas register 3 226 73 x s 4 w transmit cas register 4 226 7 4x s5 w transmit cas register 5 226 75 x s6 w transmit cas register 6 226 76 x s7 w transmit cas register 7 226 77 x s 8 w transmit cas register 8 226 7 8x s 9 w transmit cas register 9 226 7 9x s10 w transmit cas register 10 226 7a x s11 w transmit cas register 11 226 7b x s12 w transmit cas register 12 226 7c x s13 w transmit cas register 13 226 7d x s1 4 w transmit cas register 1 4 226 7e x s15 w transmit cas register 15 226 7f x s16 w transmit cas register 16 226 table 51 e1 control register address arrangement (cont?d) address register type comment page
peb 2255 falc-lh v1.3 e1 registers data sheet 1 8 3 2000-07 9.2 detailed description of e1 control registers transmit fifo (write) writing data to x fifocanbedonein 8 -bit (byte) or 16-bit (word) access. the lsb is transmitted first. u p to 32 bytes/16 words of transmit data can be written to the x fifo following a x pr (or alls) interrupt. command register (write) value after reset: 00 h rmc? receive message complete confirmation from cp u to falc ? -lh that the current frame or data block has been fetched following a rpf or rme interrupt, thus the occupied space in the rfifo can be released. rres? receiver reset the receive line interface except the clock and data recovery unit (dpll), the dcr-r circuitry, the receive framer, the one second timer and the receive signaling controller are reset. however the contents of the control registers is not deleted. rres has to be given every time after a configuration change. x rep? transmission repeat if x rep is set together with x tf (write 2 4 h to cmdr), the falc ? -lh repeatedly transmits the contents of the x fifo (1 ? 32 bytes) without hdlc framing fully transparently, i.e. without flag,crc. the cyclic transmission is stopped with a sres command or by resetting x rep. note: during cyclic transmission the xrep-bit has to be set with every write operation to cmdr. 70 x fifo x f7 x f0 (00/01) 70 cmdr rmc rres x rep x res x hf x tf x me sres (02)
peb 2255 falc-lh v1.3 e1 registers data sheet 1 84 2000-07 x res? transmitter reset the transmit framer and transmit line interface including dco- x are reset. however, the contents of the control registers is not deleted. x res has to be given every time after a configuration change. x hf? transmit hdlc frame afterhavingwrittenupto32bytestothe x fifo, this command initiates the transmission of a hdlc frame. x tf? transmit transparent frame initiates the transmission of a transparent frame without hdlc framing. x me? transmit message end indicates that the data block written last to the transmit fifo completes the current frame. the falc ? -lh can terminate the transmission operation properly by appending the crc and the closing flag sequence to the data. sres? signaling transmitter reset the transmitter of the signaling controller is reset. x fifo is cleared of any data and an abort sequence (seven 1 ' s) followed by interframe time fill is transmitted. in response to sres a x pr interrupt is generated. this command can be used by the cp u to abort a frame currently in transmission. note: the maximum time between writing to the cmdr register and the execution of the command takes 2.5 periods of the current system data rate. therefore, if the cpu operates with a very high clock rate in comparison with the falc ? -lh's clock, it is recommended that bit sis.cec should be checked before writing to the cmdr register to avoid any loss of commands. note: bits are cleared automatically except of xrep
peb 2255 falc-lh v1.3 e1 registers data sheet 1 8 5 2000-07 mode register (read/write) value after reset: 00 h mds2...0? mode select the operating mode of the hdlc controller is selected. 000? reserved 001? reserved 010? 1 byte address comparison mode (ral1,2) 011? 2 byte address comparison mode (rah1,2 and ral1,2) 100? no address comparison 101? 1 byte address comparison mode (rah1,2) 110? reserved 111? no hdlc framing mode hrac? hdlc receiver active switches the hdlc receiver to operational or inoperational state. 0? receiver inactive 1? receiver active receive address byte high register 1 (read/write) value after reset: fd h in operating modes that provide high byte address recognition, the high byte of the received address is compared with the individually programmable values in rah1 and rah2. rah1 value of the first individual high address byte bit 1 (c/r-bit) is excluded from address comparison. 70 mode mds2 mds1 mds0 hrac (03) 70 rah1 0 (0 4 )
peb 2255 falc-lh v1.3 e1 registers data sheet 1 8 6 2000-07 receive address byte high register 2 (read/write) value after reset: ff h rah2? value of second individual high address byte receive address byte low register 1 (read/write) value after reset: ff h ral1? value of first individual low address byte receive address byte low register 2 (read/write) value after reset: ff h ral2... value of the second individually programmable low address byte. interrupt port configuration (read/write) value after reset: 00 h note: unused bits have to be cleared. vis? masked interrupts visible 0 masked interrupt status bits are not visible 1 masked interrupt status bits are visible 70 rah2 (05) 70 ral1 (06) 70 ral2 (07) 70 ipc vis sci ic1 ic0 (0 8 )
peb 2255 falc-lh v1.3 e1 registers data sheet 1 8 7 2000-07 sci? status change interrupt 0 interrupts isr2.los, isr2.ais, isr3.api and isr3.lmfa16 are generated only on the rising edge of the corresponding status flag. 1 interrupts isr2.los, isr2.ais, isr3.api and isr3.lmfa16 are generated on the rising and falling edge of the corresponding status flag. ic1...0? interrupt port configuration these bits define the function of the interrupt output stage (pin int): common configuration register 1 (read/write) value after reset: 00 h sflg? enable shared flags if this bit is set, the closing flag of a preceding hdlc frame simultaneously is used as the opening flag of the following frame. 0? shared flag function disabled 1? shared flag function enabled x ts16ra? transmit time slot 16 remote alarm 0? standard operation 1? sends remote alarm in time slot 16 towards remote end by setting the y -bit in cas multiframe alignment word. this bit is logically ored with the contents of register x s1.2 ic1 ic0 function x 0 1 0 1 1 open drain output 1) push/pull output, active low push/pull output, active high 1) an external pullup resistor is required at pin int 70 ccr1 sflg x ts16ra casm eits itf rft1 rft0 (0 9 )
peb 2255 falc-lh v1.3 e1 registers data sheet 1 88 2000-07 casm? cas synchronization mode determines the synchronization mode of the channel associated signaling multiframe alignment. 0? synchronization is done in accordance to it u -t g. 732 1? synchronization is established when two consecutively correct multiframe alignment pattern are found. eits? enable internal time slot 0-31 signaling 0? internal signaling in time slots 0-31 defined via registers rtr1... 4 or ttr1... 4 is disabled. 1? internal signaling in time slots 0-31 defined via registers rtr1... 4 or ttr1... 4 is enabled. itf? interframe time fill determines the idle ( = no data to send) state of the transmit data coming from the signaling controller. 0? continuous logical ?1? is output 1? continuous flag sequences are output (?01111110? bit patterns) rft1...0... rfifo threshold level the size of the accessible part of rfifo can be determined by programming these bits. the number of valid bytes after a rpf interrupt is given in the following table: the value of rft1, 0 can be changed dynamically. ? if reception is not running or ? after the current data block has been read, but before the command cmdr.rmc is issued (interrupt controlled data transfer). rft1 rft0 size of accessible part of rfifo 0 0 1 1 0 1 0 1 32 bytes (reset value) 16 bytes 4 bytes 2bytes
peb 2255 falc-lh v1.3 e1 registers data sheet 1 89 2000-07 note: it is seen that changing the value of rft1, 0 is possible even during the reception of one frame. the total length of the received frame can be always read directly in rbcl, rbch after a rpf interrupt, except when the threshold is increased during reception of that frame. the real length can then be inferred by noting which bit positions in rbcl are reset by a rmc command (see table below): common configuration register 3 (read/write) value after reset: 00 h note: unused bits have to be cleared. pre1...0? number of preamble repetitions if preamble transmission is enabled, the preamble defined by register pre is transmitted: 00... 1 time 01... 2 times 10... 4 times 11... 8 times ept? enable preamble transmission this bit enables transmission of preamble. the preamble is started after interframe timefill transmission has been stopped and a new frame is to be transmitted. the preamble consists of an 8 -bit pattern repeated a number of times. the pattern is defined by register pre, the number of repetitions is selected by bits pre0 and pre1. note: the ? shared flag ? feature is not influenced by preamble transmission. zero bit insertion is disabled during preamble transmission. rft1 rft0 bit positions in rbcl reset by a cmdr.rmc command 0 0 1 1 0 1 0 1 rbc 4 .? 0 rbc3 ? 0 rbc1,0 rbc0 70 ccr3 pre1 pre0 ept radd rcrc x crc (0a)
peb 2255 falc-lh v1.3 e1 registers data sheet 1 9 0 2000-07 radd? receive address pushed to rfifo if this bit is set, the received hdlc address information (1 or 2 bytes, depending on the address mode selected via mode.mds0) is pushed to rfifo. see chapter 8.1 on page 169 for detailed description. rcrc? receive crc on/off if this bit is set, the received crc checksum is written to rfifo (crc-it u -t: 2 bytes). the checksum, consisting of the 2 last bytes in the received frame, is followed in the rfifo by the status information byte (contents of register rsis). the received crc checksum is additionally checked for correctness. if non-auto mode is selected, the limits for ?valid frame? check are modified ( refer to rsis.vfr and to chapter 8.1 on page 169 ). x crc? transmit crc on/off if this bit is set, the crc checksum is not generated internally. it has to be written as the last two bytes in the transmit fifo ( x fifo). the transmitted frame is closed automatically with a closing flag. note: the falc ? -lh does not check whether the length of the frame, i.e. the number of bytes to be transmitted makes sense or not. preamble register (read/write) value after reset: 00 h pre7...0? preamble register this register defines the pattern which is sent during preamble transmission (refer to ccr3). lsb is sent first. note: zero bit insertion is disabled during preamble transmission. 70 pre (0b)
peb 2255 falc-lh v1.3 e1 registers data sheet 1 9 1 2000-07 receive timeslot register 1...4 (read/write) value after reset: 00 h ,00 h ,00 h ,00 h ts0?31? timeslot register these bits define the received time slots on the system highway port rdo to be extracted to rfifo and marked. additionally these registers control the rsigm marker which can be forced high during the respective time slots independently of bit ccr1.eits. a one in the rtr1... 4 bits samples the corresponding time slots and send their data to the rfifo of the signaling controller if bit ccr1.eits is set. assignments: ts0 time slot 0 ... ts31 time slot 31 0 the corresponding time slot is not extracted and stored into the rfifo. 1?the contents of the selected time slot is stored in the rfifo. this function becomes active only if bit ccr1.eits is set. the corresponding time slot is forced high on marker pin rsigm. 70 rtr1 ts0 ts1 ts2 ts3 ts 4 ts5 ts6 ts7 (0c) rtr2 ts 8 ts 9 ts10 ts11 ts12 ts13 ts1 4 ts15 (0d) rtr3 ts16 ts17 ts1 8 ts1 9 ts20 ts21 ts22 ts23 (0e) rtr 4 ts2 4 ts25 ts26 ts27 ts2 8 ts2 9 ts30 ts31 (0f)
peb 2255 falc-lh v1.3 e1 registers data sheet 1 9 2 2000-07 transmit timeslot register 1...4 (read/write) value after reset: 00 h ,00 h ,00 h ,00 h ts0?31? transmit timeslot register these bits define the transmit time slots on the system highway to be inserted. additionally these registers control the x sigm marker which can be forced high during the respective time slots independently of bit ccr1.eits. a one in the ttr1... 4 bits inserts the corresponding time slot sourced by the x fifo in the data received on pin x di, if bit ccr1.eits is set. if sic3.ttrf is set and ccr1.eits is cleared insertion of data received on port x sigiscontrolledbythisregisters. assignments: ts0 time slot 0 ... ts31 time slot 31 0 the selected time slot is not inserted into the outgoing data stream. 1?the contents of the selected time slot is inserted into the outgoing data stream from x fifo. this function becomes active only if bit ccr1.eits is set. the corresponding time slot is forced high on marker pin x sigm. 70 ttr1 ts0 ts1 ts2 ts3 ts 4 ts5 ts6 ts7 (10) ttr2 ts 8 ts 9 ts10 ts11 ts12 ts13 ts1 4 ts15 (11) ttr3 ts16 ts17 ts1 8 ts1 9 ts20 ts21 ts22 ts23 (12) ttr 4 ts2 4 ts25 ts26 ts27 ts2 8 ts2 9 ts30 ts31 (13)
peb 2255 falc-lh v1.3 e1 registers data sheet 1 9 3 2000-07 interrupt mask register 0...5 (read/write) value after reset: ff h ,ff h ,ff h ,ff h ,ff h imr0...imr5... interrupt mask register each interrupt source can generate an interrupt signal on port int (characteristics of the output stage are defined via register ipc). a ?1? in a bit position of imr0...5 sets the mask active for the interrupt status in isr0...3 and isr5. masked interrupt statuses neither generate a signal on int, nor are they visible in register gis. moreover, they are ? not displayed in the interrupt status register if bit ipc.vis is cleared ? displayed in the interrupt status register if bit ipc.vis is set. note: after reset, all interrupts are dis abled. framer mode register 0 (read/write) value after reset: 00 h x c1... 0? transmit code serial code for the transmitter is independent to the receiver. 00... nr z (optical interface) 01... cmi (1t2b + hdb3),(seefmr3on page 210 ) 10... ami (ternary or digital dual rail interface) 11... hdb3 code (ternary or digital dual rail interface) 70 imr0 rme rfs t 8 ms rmb casc crc 4 sa6sc rpf (1 4 ) imr1 llbsc rdo alls x d ux mb x lsc x pr (15) imr2 far lfa mfar t 4 00ms ais los rar ra (16) imr3 es sec lmfa16 ais16 ra16 api rsn rsp (17) imr 4 lfa fer cer ais los cve slip ebe (1 8 ) imr5 x sp x sn (1 9 ) 70 fmr0 x c1 x c0 rc1 rc0 e x td alm frs sim (1a)
peb 2255 falc-lh v1.3 e1 registers data sheet 1 94 2000-07 rc1...0? receive code serial code for the receiver is independent to the transmitter. 00... nr z (optical interface) 01... cmi (1t2b + hdb3), (optical interface) 10... ami (ternary or digital dual rail interface) 11... hdb3 code (ternary or digital dual rail interface) e x td? extended hdb3 error detection selects error detection mode. 0? only double violations are detected. 1? extended code violation detection: 0000 strings are detected additionally. thereafter, next increment of code violation counter cvc is done after receiving additional four zeros. alm? alarm mode selects the ais alarm detection mode. 0? the ais alarm is detected according to ets300233. detection: an ais alarm is detected if the incoming data stream contains less than 3 zeros within a period of 512 bits and a loss of frame alignment is indicated. recovery: the alarm is cleared if 3 or more zeros within 512 bits are detected or the fas word is found. 1? the ais alarm is detected according to it u -t g.775 detection: an ais alarm is detected if the incoming data stream contains for two consecutive doubleframe periods (102 4 bits) less than 3 zeros for each doubleframe period (512 bits). recovery: the alarm is cleared if within two consecutive doubleframe periods 3 or more zeros for each period of 512 bits are detected. frs? force resynchronization a transition from low to high initiates a resynchronization procedure of the pulse frame and the crc-multiframe (if enabled via bit fmr2.rfs1) starting directly after the old framing candidate. note:frs is not reset automatically.
peb 2255 falc-lh v1.3 e1 registers data sheet 1 9 5 2000-07 sim? alarm simulation 0? normal operation. 1? initiates internal error simulation of ais, loss of signal, loss of synchronization, remote alarm, slip, framing errors, crc errors, and code violations. the error counters fec, cvc, cec1 are incremented. framer mode register 1 (read/write) value after reset: 00 h mfcs? multiframe force resynchronization only valid if crc multiframe format is selected (fmr2.rfs1/0 = 10). a transition from low to high initiates the resynchronization procedure for crc-multiframe alignment without influencing doubleframe synchronous state. in case, ?automatic force resynchronization? (fmr1.afr) is enabled and multiframe alignment can not be regained, a new search of doubleframe (and crc multiframe) is automatically initiated. note:mfcs is not reset automatically. afr? automatic force resynchronization only valid if crc multiframe format is selected (fmr2.rfs1/0 = 10). if this bit is set, a search of doubleframe alignment is automatically initiated if two multiframe patterns with a distance of n 2 ms have not been found within a time interval of 8 ms after doubleframe alignment has been regained. ensa? enable s a -bit access via register x sa4...8 0? normal operation. the s a -bit information is taken from bits x sw. xy 0? 4 and written to bits rsw.r y 0? 4 . 1? s a -bit register access. the s a -bit information is taken from the registers x sa 4 ... 8 . in addition, the received information is written to registers rsa 4 ... 8 . transmitting of the contents of registers x sa 4 ... 8 is disabled if one of time slot 0 transparent modes is enabled ( x sp.tt0 or tswm.sa 4 ... 8 ). 70 fmr1 mfcs afr ensa pmod x fs ecm imod x ais (1b)
peb 2255 falc-lh v1.3 e1 registers data sheet 1 9 6 2000-07 pmod? pcm mode for e1 application this bit must be set low. switching from e1 to t1 or vice versa the device needs up to 10 s to settle up to the internal clocking. 0? pcm 30 or e1 mode. 1? pcm 2 4 or t1 mode. x fs? transmit framing select selection of the transmit framing format could be done independent of the receive framing format. 0? doubleframe format enabled. 1? crc 4 -multiframe format enabled. ecm? error counter mode the function of the error counters is determined by this bit. 0 before reading an error counter the corresponding bit in the disable error counter register (dec) has to be set. in 8 bit access the low byte of the error counter should always be read before the high byte. the error counters are reset with the rising edge of the corresponding bits in the dec register. 1? every second the error counters are latched and then automatically be reset. the latched error counter state should be read within the next second. reading the error counter during updating should be avoided (do not access an error counter within 2 s before or after the one-second interrupt occurs). imod? select system interface mode 0... 4 .0 9 6mbit/s 1... 2.0 48 mbit/s x ais? transmit ais towards remote end sends ais via ports x l1, x l2, x oid towards the remote end. the outgoing data stream which could be looped back via the local loop to the system interface is not affected.
peb 2255 falc-lh v1.3 e1 registers data sheet 1 9 7 2000-07 framer mode register 2 (read/write) value after reset: 00 h rfs1... 0... receive framing select 00? doubleframe format 01? doubleframe format 10? crc 4 multiframe format 11? crc 4 multiframe format with modified crc 4 multiframe alignment algorithm (interworking according to it u -t g.706 annex b). setting of fmr3.e x tiw changes the reaction after the 4 00 ms timeout. rtm? receive transparent mode setting this bit disconnects control of the internal elastic store from the receiver. the elastic store is now in a ?free running? mode without any possibility to update the time slot assignment to a new frame position in case of re-synchronization of the receiver. this function can be used in conjunction with the ?disable ais to system interface? feature (fmr2.dais) to realize undisturbed transparent reception. this bit should be enabled in case of unframed data reception mode. after resetting rtm to 0, the elastic buffer is adjusted after the next resynchronization. dais? disable ais to system interface 0? ais is automatically inserted into the data stream to rdo if falc ? -lh is in asynchronous state. 1? automatic ais insertion is disabled. furthermore, ais insertion can be initiated by programming bit fmr2.sais. sais? send ais towards system interface sends ais via output rdo towards system interface. this function is not influenced by bit fmr2.dais. plb? payload loopback 0? normal operation. payload loop is disabled. 1... the payload loopback loops the data stream from the receiver section back to transmitter section. looped data is output on pin rdo. data received on port x di, x sig, s y p x and x mfs is 70 fmr2 rfs1 rfs0 rtm dais sais plb a x ra almf (1c)
peb 2255 falc-lh v1.3 e1 registers data sheet 1 98 2000-07 ignored. with x sp.tt0 = 1 timeslot 0 is also looped. if x sp.tt0 = 0 timeslot 0 is generated internally. ais is sent immediately on port rdo by setting the fmr2.sais bit. it is recommended to write the actual value of x c1 into this register once again, because a write access to register x c1 sets the read/write pointer of the transmit elastic buffer into its optimal position to ensure a maximum wander compensation (the write operation forces a slip). a x ra? automatic transmit remote alarm 0? normal operation 1? the remote alarm bit is set automatically in the outgoing data stream if the receiver is in asynchronous state (frs0.lfa bit is set). in synchronous state the remote alarm bit is reset. additionally in multiframe format fmr2.rfs1 = 1and fmr3.e x tiw = 1 and the 4 00 ms timeout has elapsed, the remote alarm bit is active in the outgoing data stream. in multiframe synchronous state the outgoing remote alarm bit is cleared. almf? automatic loss of multiframe 0? normal operation 1? the receiver searches a new basic framing and multiframing if more than 9 1 4 crc errors have been detected in a time interval of one second. the internal 9 1 4 crc error counter is reset if the multiframe synchronization is found. incrementing the counter is only enabled in the multiframe synchronous state.
peb 2255 falc-lh v1.3 e1 registers data sheet 1 99 2000-07 channel loop back register (read/write) value after reset: 00 h spn? select additional optical pin functions together with bit lim3.es y the functionality of pin 8 0 is defined: programming of loop.spn and lim3.es y and the corresponding pin function is shown below. spn/es y : 00? function of pin 8 0 x sig: if sic3.ttrf = 1, transmit data from the system interface. internal multiplexing with the x di data stream is controlled by x sigm. no input function defined for sic3.ttrf = 0. 01? function of pin 8 0s y nc2: external synchronization input for the dco- x circuitry 10? function of pin 8 0roid:receiveopticalinterfacedata (input) and pin 6 8 : x mfb/ x oid transmit optical interface data (output). at the same time data received on pin 2 are ignored, data on pin x oid (pin 15) are undefined. transmit data is clocked off with the positive transition of x cl k . after reset the transmit multiframe begin marker is output on pin 6 8 . 11? function of pin 8 0 x sig: the signaling information from thetransmitsysteminterfaceisreceivedonpin x sig. bit fmr5.eibr should be cleared to disable internal signaling access from registers x s1...16. the signaling information from the line interface is transmitted on pin rsig. sfm? single frame mode setting this bit reduces the receive speech memory from two to one frame length. in this case, clocks scl k r and rcl k have to be phase locked to avoid slip conditions. however, slip detection still works but without any influence on data transmission. note:this mode is not recommended, but possible to be compatible with falc ? 54. newer falc devices (e.g. falc ? 56, quadfalc tm ) don ? t support this any more. 70 loop spn sfm eclb cla 4 cla3 cla2 cla1 cla0 (1d)
peb 2255 falc-lh v1.3 e1 registers data sheet 200 2000-07 eclb? enable channel loop back 0... disables the channel loop back. 1... enables the channel loop back selected by this register. cla4...0? channel address for loop back cla = 0?31 selects the channel. during looped back the contents of the assigned outgoing channel on ports x l1/ x dop/ x oid and x l2/ x don is equal to the idle channel code programmed at register idle. transmit service word pulseframe (read/write) value after reset: 00 h x sis? spare bit for international use first bit of the service word. only significant in doubleframe format. if not used, this bit should be fixed to ?1?. if one of the time slot 0 transparent modes is enabled (bit x sp.tt0, or tswm.tsis), bit x sw. x sis is ignored. x tm? transmit transparent mode 0?ports s y p x / x mfs define the frame/multiframe begin on the transmit system highway. the transmitter is usually synchronized on this externally sourced frame boundary and generates the fas bits according to this framing. any change of the transmit time slot assignment or a transmit slip subsequently produces a change of the fas bit positions. 1? disconnects the control of the transmit system interface from the transmitter. the transmitter is now in a free running mode without any possibility to update the multiframe position. the framing (fas bits) generated by the transmitter are not disturbed (in case of changing the transmit time slot assignment or transmit slip) by the transmit system highway unless register x c1 is written. u seful in loop-timed applications. for correct operation the transmit elastic buffer (2 frames, sic1. x bs1/0 = 10) has to be enabled. 70 x sw x sis x tm x ra xy 0 xy 1 xy 2 xy 3 xy4 (1e)
peb 2255 falc-lh v1.3 e1 registers data sheet 201 2000-07 x ra? transmit remote alarm 0? normal operation. 1? sends remote alarm towards remote end by setting bit 3 of the service word. if time slot 0 transparent mode is enabled via bit x sp.tt0 or tswm.tra bit is set, bit x sw. x ra is ignored. x y0?4? spare bits for national use (y-bits, s n -bits, s a -bits) these bits are inserted in the service word of every other pulseframe if s a -bit register access is disabled (fmr1.ensa = 0). if not used, they should be fixed to ?1?. if one of the time slot 0 transparent modes is enabled (bit x sp.tt0 or tswm.tsa 4 ... 8 ), bits x sw. xy 0? 4 is ignored. transmit spare bits (read/write) value after reset: 00 h x ap? transmit auxiliary pattern towards remote end 0? normal operation. 1? a one in this bit position causes the transmitter to send an alternating pattern 101010... towards the remote end. fmr1. x ais = 1 overwrites the alternating pattern by a continuous one bit stream. casen? channel associated signaling enable 0? normal operation. 1? a one in this bit position causes the transmitter to send the cas information stored in the x s1...16 registers in the corresponding time slots. tt0? time slot 0 transparent mode 0? normal operation. 1? all information for time slot 0 on port x di is inserted in the outgoing pulseframe. all internal information of the falc ? -lh (framing, crc, s a /s i bit signaling, remote alarm) is ignored. this function is mainly useful for system test applications (test 70 x sp x ap casen tt0 ebp a x s x sif x s13 x s15 (1f)
peb 2255 falc-lh v1.3 e1 registers data sheet 202 2000-07 loops). priority sequence of transparent modes: x sp.tt0 > tswm. ebp? e-bit polarity 0? in the basic framing or multiframe asynchronous state the e-bit is cleared. 1? in the basic framing or multiframe asynchronous state the e-bit is set. if automatic transmission of sub-multiframe status is enabled by setting bit x sp.a x s and the receiver has been lost multiframe synchronization, the e bit with the programmed polarity is inserted automatically in s i -bit position of every outgoing crc multiframe (under the condition that time slot 0 transparent mode and transparent s i bit in service word are both disabled). a x s? automatic transmission of submultiframe status only applicable to crc multiframe. 0? normal operation. 1? information of submultiframe status bits rsp.si1 and rsp.si2 is inserted automatically in s i -bit positions of the outgoing crc multiframe (rsp.si1 s i -bit of frame 13 ; rsp.si2 s i -bit of frame 15). contents of x sp. x s13 and x sp. x s15 is ignored. if one of the time slot 0 transparent modes x sp.tt0 or tswm.tsis is enabled, bit x sp.a x s has no function. x sif? transmit spare bit for international use (fas word) first bit in the fas word. only significant in doubleframe format. if not used, this bit should be fixed to ?1?. if one of the time slot 0 transparent modes is enabled (bits x sp.tt0, or tswm.tsif), bit x sp. x sif is ignored. x s13? transmit spare bit (frame 13, crc-multiframe) first bit in the service word of frame 13 for international use. only significant in crc-multiframe format. if not used, this bit should be fixedto?1?.theinformationof x sp. x s13 is shifted into internal transmission buffer with beginning of the next following transmitted crc multiframe. if automatic transmission of submultiframe status is enabled via bit x sp.a x s, or, if one of the time slot 0 transparent modes x sp.tt0 or tswm.tsis is enabled, bit x sp. x s13 is ignored.
peb 2255 falc-lh v1.3 e1 registers data sheet 203 2000-07 x s15? transmit spare bit (frame 15, crc-multiframe) first bit in the service word of frame 15 for international use. only significant in crc-multiframe format. if not used, this bit should be fixedto?1?.theinformationof x sp. x s15 is shifted into internal transmission buffer with beginning of the next following transmitted crc multiframe. if automatic transmission of submultiframe status is enabled via bit x sp.a x s, or, if one of the time slot 0 transparent modes x sp.tt0 or tswm.tsif is enabled, bit x sp. x s15 is ignored. transmit control 0 (read/write) value after reset: 00 h sa8e...4e sa bit signaling enable 0? standard operation. 1? by setting this bit it is possible to send/receive a lapd protocol in any combination of the sa 8 ...sa 4 bit positions in the outgoing/incoming data stream. the on chip signaling controller has to be configured in the hdlc/lapd mode. in transmit direction together with these bits the tswm.tsa 8 - 4 bits must be set to enable transmission to the remote end transparently through the falc ? -lh. x co2...0? transmit clock slot offset initial value loaded into the transmit bit counter at the trigger edge of scl kx when the synchronous pulse on port s y p x is active. refer to register x c1. x co0 must be cleared if sic1.s x sc is set. transmit control 1 (read/write) value after reset: 00 h a write access to this address resets the transmit elastic buffer to its basic starting position. therefore, updating the value should only be done when the falc ? -lh is 70 x c0 sa 8 e sa7e sa6e sa5e sa 4 e x co2 x co1 x co0 (20) 70 x c1 x cos x to5 x to 4x to3 x to2 x to1 x to0 (21)
peb 2255 falc-lh v1.3 e1 registers data sheet 20 4 2000-07 initialized or when the buffer should be centered. as a consequence a transmit slip occurs. x cos? transmit clock offset shift only valid if sic1.s x sc = 0. 0? the delay t between the beginning of time slot 0 and the initial edge of scl kx (after s y p x goes active) is an even number in the range of 0 to 1022 scl kx cycles. 1? the delay t is an odd number in the range of 1 to 1023 scl kx cycles. x to5...0? transmit time slot offset initial value loaded into the transmit time slot counter at the trigger edge of scl kx when the synchronous pulse on port s y p x is active. receive control 0 (read/write) value after reset: 00 h rcos? receive clock offset shift 0? the delay t between the beginning of time slot 0 and the initial edge of scl k r(afters y pr goes active) is an even number in the range of 0 to 1022 scl k rcycles. 1? the delay t is an odd number in the range of 1 to 1023 scl k r cycles. sics? system interface channel select only applicable for pcm highway configuration 8 mhz and 4 mbit/s 0? received data is output on port rdo in the first channel phase. data line rdo is tristated in the second channel phase. data on pin x di is sampled in the first channel phase only. data on x di in the second channel phase is ignored. 1? received data is output on port rdo in the second channel phase. data line rdo is tristated in the first channel phase. data on pin x di is sampled in the second channel phase only. data on x di in the first channel phase is ignored. 70 rc0 rcos sics crci x crci rdis rco2 rco1 rco0 (22)
peb 2255 falc-lh v1.3 e1 registers data sheet 205 2000-07 crci? automatic crc4 bit inversion if set, all crc bits of one outgoing submultiframe are inverted in case a crc error is flagged for the previous received submultiframe. this function is logically ored with rc0. x crci. x crci? transmit crc4 bit inversion if set, the crc bits in the outgoing data stream are inverted before transmission. this function is logically ored with rc0.crci. rdis? receive data input sense only applicable for dual rail mode (lim1.drs = 1). 0? inputs: rdip, rdin active low, input roid is active high 1? inputs: rdip, rdin active high, input roid is active low rco2...0? receive clock slot offset/receive frame marker offset depending on bit sic2.srfso this bit enables different functions: receive clock-slot offset (sic2.srfso = 0) initial value loaded into the receive bit counter at the trigger edge of scl k r when the synchronous pulse on port s y pr is active. receive frame marker offset (sic2.srfso = 1) offset programming of the receive frame marker which is output on port s y pr . the receive frame marker could be activated during any bit position of the current frame. calculation of the value x of the ?receive counter offset? register rc1/0 depends on the bit position bp which should be marked and scl k r: x= (2 + 2 bp) mod 512, for scl k r = 2.0 48 mhz.
peb 2255 falc-lh v1.3 e1 registers data sheet 206 2000-07 receive control 1 (read/write) value after reset: 00 h swd ? service word condition disable 0? standard operation. three or four consecutive incorrect service words (depending on bit rc1.as y4 ) causes loss of synchronization. 1? errors in service words have no influence when in synchronous state. however, they are used for the resynchronization procedure. asy4 ? select loss of sync condition 0? standard operation. three consecutive incorrect fas words or three consecutive incorrect service words causes loss of synchronization. 1? four consecutive incorrect fas words or four consecutive incorrect service words causes loss of synchronization. the service word condition may be disabled via bit rc1.swd. rto5...0? receive time slot offset/receive frame marker offset depending on bit sic2.srfso this bit enables different functions: receive time slot offset (sic2.srfso = 0) initial value which is loaded into the receive time slot counter at the trigger edge of scl k r when the synchronous pulse on port s y pr is active. receive frame marker offset (sic2.srfso = 1) offset programming of the receive frame marker which is output on port s y pr . the receive frame marker could be activated during any bit position of the current frame. calculation of the value x of the ?receive counter offset? register rc1/0 depends on the bit position bp which should be marked and scl k r: x= (2 + 2bp)mod512 ,forscl k r = 2.0 48 mhz. 70 rc1 swd as y4 rto5 rto 4 rto3 rto2 rto1 rto0 (23)
peb 2255 falc-lh v1.3 e1 registers data sheet 207 2000-07 transmit pulse-mask 0...2 (read/write) value after reset: 9 c h ,03 h ,00 h the transmit pulse shape which is defined in it u -t g.703 is output on pins x l1 and x l2. the level of the pulse shape can be programmed via registers x pm2...0tocreatea custom waveform. in order to get an optimized pulse shape for the external transformers each pulse shape is internally divided into four sub pulse shapes. in each sub pulse shape a programmed 5 bit value defines the level of the analog voltage on pins x l1/2. together four 5 bit values have to be programmed to form one complete transmit pulse shape. the four 5 bit values are sent in the following sequence: x p0 4 -00: first pulse shape level x p1 4 -10: second pulse shape level x p2 4 -20: third pulse shape level x p3 4 -30: fourth pulse shape level changing the lsb of each subpulse in registers x pm2...0 changes the amplitude of the differential voltage on x l1/2 by approximately 110 mv. example:120 ? interface and wired as shown in figure 23 on page 79 . x pm0 4 -00: 1d h or 2 9 decimal x pm1 4 -10: 1d h or 2 9 decimal x pm2 4 -20: 00 h x pm3 4 -30: 00 h programming values for x pm0...2: bd h ,03 h ,00 h x lhp? transmit line high power 0? normal operation 1? with this bit the output current capability of the transmit line x l1 and x l2 can be influenced. connecting low impedances to the outputs x l1/ x l2 this bit should be set to increase the possible output current. setting this bit has no influence on the voltage levels of the pulse shape. 70 x pm0 x p12 x p11 x p10 x p0 4x p03 x p02 x p01 x p00 (2 4 ) x pm1 x p30 x p2 4x p23 x p22 x p21 x p20 x p1 4x p13 (25) x pm2 x lhp x lt da x lt x p3 4x p33 x p32 x p31 (26)
peb 2255 falc-lh v1.3 e1 registers data sheet 20 8 2000-07 x lt? transmit line tristate 0? normal operation 1? transmit line x l1/ x l2 or x dop/ x don are switched into high impedance state. if this bit is set the transmit line monitor status information is frozen. da x lt... disable automatic tristating of x l1/2 0... normal operation. if a short is detected on pins x l1/2 the transmit line monitor sets the x l1/2 outputs into a high impedance state. 1... if a short is detected on x l1/2 pins automatic setting these pins into a high impedance (by the x l-monitor) state is disabled. transparent service word mask (read/write) value after reset: 00 h tswm7...0? transparent service word mask tsis? transparent s i -bit in service word 0? the s i -bit is generated internally. 1? the s i -bit in the service word is taken from port x di and transparently passed through the falc ? -lh without any changes. the internal information of the falc ? -lh (register x sw) is ignored. tsif? transparent s i bit in fas word 0? the s i -bit is generated internally. 1? the s i -bit in the fas word is taken from port x di and routed transparently through the falc ? -lh without any changes. the internal information of the falc ? -lh (register x sw) is ignored. 70 tswm tsis tsif tra tsa 4 tsa5 tsa6 tsa7 tsa 8 (27)
peb 2255 falc-lh v1.3 e1 registers data sheet 20 9 2000-07 tra? transparent remote alarm 0? the remote alarm bit is generated internally. 1? the a bit is taken from port x di and routed transparently through the falc ? -lh without any changes. the internal information of the falc ? -lh (register x sw) is ignored. tsa4?8... transparent sa4...8 bit 0? the sa 4 ... 8 bits are generated internally. 1? the sa 4 ... 8 bits are taken from port x di or from the internal signaling controller if enabled and transparently passed through the falc ? -lh without any changes. the internal information of the falc ? -lh (registers x sw and x sa 4 ... 8 )is ignored. idle channel code register (read/write) value after reset: 00 h idl7?0? idle channel code if channel loop back is enabled by programming loop.eclb = 1, the contents of the assigned outgoing channel on ports x l1/ x l2 or x dop/ x don is set equal to the idle channel code selected by this register. additionally, the specified pattern overwrites the contents of all channels selected via the idle channel registers icb1?icb 4 .idl7is transmitted first. 70 idle idl7 idl0 (2 9 )
peb 2255 falc-lh v1.3 e1 registers data sheet 210 2000-07 transmit sa4...8 register (read/write) value after reset: 00 h ,00 h ,00 h ,00 h ,00 h x sa8? x sa4? transmit s a -bit data the sa-bit register access is enabled by setting bit fmr1.ensa = 1. with the transmit multiframe begin an interrupt isr1. x mb is generated and the contents of these registers x sa 4 ... 8 is copied into a shadow register. the contents is subsequently sent out in the service words of the next outgoing crc multiframe (or doubleframes) if none of the time slot 0 transparent modes is enabled. x s 4 0 is sent out in bit position 4 in frame 1, x s 4 7 in frame 15. the transmit multiframe begin interrupt x mb request that these registers should be serviced. if requests for new information are ignored, current contents is repeated. framer mode register 3 (read/write) value after reset: 00 h x ld? transmit llb down code 0? normal operation. 1? a one in this bit position causes the transmitter to replace normal transmit data with the llb down (deactivate) code continuously until this bit is reset. the llb down code is optionally overwritten by the timeslot 0 depending on bit 70 x sa 4 x s 4 7 x s 4 6 x s 4 5 x s 44 x s 4 3 x s 4 2 x s 4 1 x s 4 0 (2a) x sa5 x s57 x s56 x s55 x s5 4x s53 x s52 x s51 x s50 (2b) x sa6 x s67 x s66 x s65 x s6 4x s63 x s62 x s61 x s60 (2c) x sa7 x s77 x s76 x s75 x s7 4x s73 x s72 x s71 x s70 (2d) x sa 8 x s 8 7 x s 8 6 x s 8 5 x s 84 x s 8 3 x s 8 2 x s 8 1 x s 8 0 (2e) 70 fmr3 x ld x l u cmi sa6s y cfr z e x tiw (2f)
peb 2255 falc-lh v1.3 e1 registers data sheet 211 2000-07 lcr1.llbf. for correct operation bit fmr3. x l u must be cleared. x lu? transmit llb up code 0? normal operation. 1? a one in this bit position causes the transmitter to replace normal transmit data with the llb u p code continuously until this bit is reset. the llb u p code is overwritten by the timeslot 0 depending on bit lcr1.llbf. for correct operation bit fmr3. x ld must be cleared. cmi? select cmi precoding only valid if cmi code (fmr0. x c1/0 = 01) is selected. this bit defines the cmi precoding and influences only the transmit data and not the receive data. 0? cmi with hdb3 precoding 1? cmi without hdb3 precoding sa6sy? receive sa6 access synchronous mode only valid if multiframe format (fmr2.rfs1/0 = 1x) is selected. 0? the detection of the predefined sa6 bit pattern (refer to chapter sa6 bit detection according to ets 300233) is done independently of the multiframe synchronous state. 1? the detection of the sa6 bit pattern is done synchronously to the multiframe. cfr z ? enable cas freeze output this bit selects the function of pin rfsp q . 0? the receive frame synchronous pulse is output on pin rfsp q . 1? the synchronous status of the integrated cas controller (frs1.ts16lfa) is output on pin rfsp .ifthecas synchronizer lost its synchronization this pin is set high. e x tiw? extended crc4 to non crc4 interworking only valid in multiframe format. this bit selects the reaction of the synchronizer after the 4 00 ms timeout has been elapsed and starts transmitting a remote alarm if fmr2.a x ra is set. 0? the crc 4 to non crc 4 interworking is done as described in it u -t g. 706 annex b.
peb 2255 falc-lh v1.3 e1 registers data sheet 212 2000-07 1? the interworking is done according to it u -t g. 706 with the exception that the synchronizer still searches for the multiframing even if the 4 00 ms timer is expired. switching into doubleframe format is disabled. if fmr2.a x ra is set the remote alarm bit is active in the outgoing data stream until the multiframe is found. idle channel register (read/write) value after reset: 00 h ,00 h ,00 h ,00 h ic0?31? idle channel selection bits these bits define the channels (time slots) of the outgoing pcm frame to be altered. assignments: ic0 time slot 0 ic1 time slot 1 ... ic31 time slot 31 0? normal operation. 1? idle channel mode. the contents of the selected time slot is overwritten by the idle channel code defined via register idle. note: although time slot 0 can be selected by bit ic0, its contents is only altered if the transparent mode is selected (xsp.tt0). 70 icb1 ic0 ic1 ic2 ic3 ic 4 ic5 ic6 ic7 (30) icb2 ic 8 ic 9 ic10 ic11 ic12 ic13 ic1 4 ic15 (31) icb3 ic16 ic17 ic1 8 ic1 9 ic20 ic21 ic22 ic23 (32) icb 4 ic2 4 ic25 ic26 ic27 ic2 8 ic2 9 ic30 ic31 (33)
peb 2255 falc-lh v1.3 e1 registers data sheet 213 2000-07 line interface mode 0 (read/write) value after reset: 00 h x fb? transmit full bauded mode only applicable for dual rail mode (bit lim1.drs = 1). 0?output signals x dop/ x don are half bauded (normal operation). 1?output signals x dop/ x don are full bauded. note: if cmi coding is selected (fmr0.xc1/0=01) this bit has to be cleared. x dos? transmit data out sense only applicable for dual rail mode (bit lim1.drs = 1) 0? output signals x dop/ x don are active low. output x oid is active high (normal operation). 1? output signals x dop/ x don are active high. output x oid is active low. note: if cmi coding is selected (fmr0.xc1/0=01) this bit has to be cleared. scl1?0? select clock output 00? output frequency at pin cl kx :20 48 khz active high 01? output frequency at pin cl kx :20 48 khz active low 10? output frequency at pin cl kx : 4 0 9 6 khz active high 11? output frequency at pin cl kx : 4 0 9 6khzactivelow eqon? receive equalizer on 0? -10 db receiver: short haul mode 1? - 4 3 db receiver, long haul mode elos enable loss of signal 0? normal operation. the extracted receive clock is output via pin rcl k . 1? in case of loss of signal (frs0.los = 1) the rcl k is set high. if frs0.los = 0 the received clock is output via rcl k . 70 lim0 x fb x dos scl1 scl0 e q on elos ll mas (3 4 )
peb 2255 falc-lh v1.3 e1 registers data sheet 21 4 2000-07 ll? local loop 0? normal operation 1? local loop active. the local loopback mode disconnects the receive lines rl1/rl2 or rdip/rdin from the receiver. instead of the signals coming from the line the data provided by system interface are routed through the analog receiver back to the system interface. the unipolar bit stream is transmitted undisturbedly on the line. receiver and transmitter coding must be identical. operates in analog and digital line interface mode. in analog line interface mode data is transferred through the complete analog receiver. mas? master mode 0? slave mode 1 master mode on. setting this bit the dco-r circuitry is frequency synchronized with the clock (2.0 48 mhz) supplied by s y nc. if this pin is connected to vss the dco-r circuitry is centered and no receive jitter attenuation is performed. the generated clocks are stable. line interface mode 1 (read/write) value after reset: 00 h efsc? enable frame synchronization pulse 0? the transmit clock is output via pin x cl k . 1? pin x cl k provides a 8 khz frame synchronization pulse which is active high for one 2 mhz cycle (pulse width = 488 ns). ril2?0? receive input threshold only valid if analog line interface in short haul mode is selected (lim0.e q on = 0 and lim1.drs = 0). loss of signal is declared if the voltage between pins rl1 and rl2 drops below the limits programmed via bits ril2...0 and the received data stream has no transition for a period defined in the pcd register. the threshold where no signal is declared is programmable by the ril2...0 bits, see table 58 " dc parameters " on page 336 for detail. note: lim1.ril(2:0) must be programmed before lim0.eqon = 1 is set. 70 lim1 efsc ril2 ril1 ril0 tcd1 jatt rl drs (35)
peb 2255 falc-lh v1.3 e1 registers data sheet 215 2000-07 tcd1? transmit clock generation dco- x 0? the transmit clock is sourced by the dco- x circuitry, if the transmit elastic buffer is enabled. reference clock is x tal3. 1? the transmit clock is sourced by the dco- x circuitry, if the transmit elastic buffer is enabled. reference clock is x tal1. dco-r cannot be used in this configuration. jatt?rl... transmit jitter attenuator/remote loop 00? normal operation. the transmit jitter attenuator is disabled. transmit data bypasses the buffer. 01? remote loop active without transmit jitter attenuator enabled. transmit data bypasses the buffer. 10? transmit slicer active. falc5 4 compatibility: transmit data received on port x di is first written into the transmit jitter attenuator and then sent jitter free on ports x l1/2 or x dop/n or x oid. for falc-lh the same function even with a better support in case of slips is also provided if bits are set to sic1. x bs1/0 = 10. 11? remote loop and jitter attenuator active. received data from pins rl1/2 or rdip/n or roid is sent ?jitter free? on ports x l1/ 2or x dop/n or x oid. the dejittered clock is generated by the dco- x circuitry. drs? dual rail select 0? the ternary interface is selected. multifunction ports rl1/2 and x l1/2 become analog in/outputs. 1? the digital dual rail interface is selected. received data is latched on multifunction ports rdip/rdin while transmit data is output on pins x dop/ x don.
peb 2255 falc-lh v1.3 e1 registers data sheet 216 2000-07 pulse count detection register (read/write) value after reset: 00 h pcd7?0? pulse count detection a los alarm is detected if the incoming data stream has no transitions for a programmable number t consecutive pulse positions. the number t is programmable via the pcd register and canbecalculatedasfollows: t = 16 (n + 1) ; with 0 n 255. the maximum time is: 256 x 16 x 488 ns = 2 ms. every detected pulse resets the internal pulse counter. the counter is clocked with the receive clock rcl k . pulse count recovery (read/write) value after reset: 00 h pcr7?0? pulse count recovery a los alarm is cleared if a pulse density is detected in the received bit stream. the number of pulses m which must occur in the predefined pcd time interval is programmable via the pcr register and can be calculated as follows: m = n + 1 ; with 0 n 255. the time interval starts with the first detected pulse transition. with every received pulse a counter is incremented and the actual counter is compared with the contents of pcr register. if the pulse number is thepcrvaluethelosalarmisreset ; otherwise the alarm stays active. in this case the next detected pulse transition starts a new time interval. 70 pcd pcd7 pcd0 (36) 70 pcr pcr7 pcr0 (37)
peb 2255 falc-lh v1.3 e1 registers data sheet 217 2000-07 line interface mode 2 (read/write) value after reset: 00 h dja2? digital jitter attenuation dco- x 0? jitter attenuation of the transmit clock is done using an external pullable crystal between pins x tal3/ 4 1? jitter attenuation of the transmit clock is done without using an external pullable crystal between pins x tal3/ 4 . only a free running 16.3 84 -mhz clock has top be provided at x tal3 ( + /- 50 ppm). dja1? digital jitter attenuation dco-r 0? jitter attenuation of the system/transmit clock is done using an external pullable crystal between pins x tal1/2 1? jitter attenuation of the system/transmit clock is done without using an external pullable crystal between pins x tal1/2. only a free running 16.3 84 -mhz clock has top be provided at x tal1 ( + /- 50 ppm). scf? select corner frequency of dco-r setting this bit reduces the corner frequency of the dco-r circuit by the factor of ten to 0.2 hz. note: reducing the corner frequency of the dco-r circuitry increases the synchronization time before the frequencies are synchronized. elt? enable loop-timed 0? normal operation. 1? transmit clock is generated from the clock supplied by x tal3/ 4 which is synchronized with the extracted receive route clock. in this configuration the transmit elastic buffer has to be enabled. refer to register x sw. x tm. 70 lim2 dja2 dja1 scf elt los2 los1 (3 8 )
peb 2255 falc-lh v1.3 e1 registers data sheet 21 8 2000-07 los2...1? loss of signal recovery condition 00? the los alarm is cleared if the predefined pulse density (register pcr) is detected during the time interval which is defined by register pcd. 01? additionally to the recovery condition described above a los alarm is only cleared if the pulse density is fulfilled and no more than 15 contiguous zeros are detected during the recovery interval. (according to tr-nwt 499 ). 10? clearing a los alarm is done if the pulse density is fulfilled and no more than 99 contiguous zeros are detected during the recovery interval. (according to tr-nwt 8 20). 11? not assigned. loop code register 1 (read/write) value after reset: 00 h eprm? enable pseudo random bit sequence monitor 0? pseudo random bit sequence (prbs) monitor is disabled. 1? prbs monitor is enabled. setting this bit enables incrementing the cec2 error counter with each detected prbs bit error. with any change of state of the prbs internal synchronization status an interrupt isr1.llbsc is generated. the current status of the prbs synchronizer is indicated by bit rsp.llbad. the expected prbs sequence has to be selected by bit lcr1.llbp. the prbs status signal is output on pin rfsp ,if fmr3.cfr z= 0 and lcr1.eprm = 1. it is set high, if the prbs monitor is in synchronous state. x prbs? transmit pseudo random bit sequence a one in this bit position enables transmitting of a pseudo random bit sequence to the remote end. depending on pit llbp the prbs is generated according to 2 15 -1 or 2 20 -1 with a maximum-1 4 -zero restriction ( it u -t o. 151). 70 lcr1 eprm x prbs ldc1 ldc0 lac1 lac0 fllb llbp (3 9 )
peb 2255 falc-lh v1.3 e1 registers data sheet 21 9 2000-07 ldc1?0... length deactivate (down) code these bits defines the length of the user programmable llb deactivate code which is programmable in register lcr2. 00? length: 5 bit 01? length: 6 bit 10? length: 7 bit 11? length: 8 bit if a shorter pattern length is required, select a multiple of the required length and repeat the pattern in lcr2. lac1?0... length activate (up) code these bits defines the length of the user programmable llb activate code which is programmable in register lcr3. 00? length: 5 bit 01? length: 6 bit 10? length: 7 bit 11? length: 8 bit if a shorter pattern length is required, select a multiple of the required length and repeat the pattern in lcr3. fllb? framed line loopback/invert prbs depending on bit lcr1. x prbs this bit enables different functions: lcr1. x prbs = 0: 0? the line loopback code is transmitted including framing bits. 1? the line loopback code is transmitted unframed. invert prbs lcr1. x prbs = 1: 0? the generated prbs is transmitted not inverted. 1? the prbs is transmitted inverted.
peb 2255 falc-lh v1.3 e1 registers data sheet 220 2000-07 llbp? line loopback pattern lcr1. x prbs = 0 0? fixed line loopback code : 001 (loop down) or 00001 (loop up). 1? enable user programmable line loopback code via register lcr2/3. lcr1. x prbs = 1 or lcr1.eprm = 1 0? 2 15 -1 1? 2 20 -1 loop code register 2 (read/write) value after reset: 00 h ldc7?0? line loopback deactivate code if enabled by bit fmr3. x ld the llb deactivate code is repeated automatically until the llb generator is stopped. transmit data is overwritten by the llb code. ldc0 is transmitted last. if the selected code length is less than 8 bit, the leftmost bits of lcr2 are ignored. for correct operations bit lcr1. x prbs has to be cleared. loop code register 3 (read/write) value after reset: 00 h lac7?0? line loopback activate code if enabled by bit fmr3. x l u the llb activate code is repeated automatically until the llb generator is stopped. transmit data is overwritten by the llb code. lac0 is transmitted last. if the selected code length is less than 8 bit, the leftmost bits of lcr3 are ignored. for correct operations bit lcr1. x prbs has to be cleared. 70 lcr2 ldc7 ldc0 (3a) 70 lcr3 lac7 lac0 (3b)
peb 2255 falc-lh v1.3 e1 registers data sheet 221 2000-07 system interface control 1 (read/write) value after reset: 00 h srsc? select receive system clock 0? expected frequency on pin scl k r: 8 .1 9 2mhz calculation of delay time t (scl k r cycles) depends on the value x of the ?receive counter offset? register rc1/0 and of the programming of rc0.rcos. delay t is an even number in the range of 0 to 1022: rcos = 0: x= 5 ? t/2 if x= 517 ? t/2 if delay t is an odd number in the range of 1 to 1023: rcos = 1: x= 5 ? (t ? 1)/2 if x= 517 ? (t ? 1)/2 if 1? expected frequency on pin scl k r: 2.0 48 mhz calculation of delay time t (scl k r cycles) depends on the value x of the ?receive counter offset? register rc1/0: t = (260 ? x/2) mod 256 delay time t = time between beginning of time slot 0 at rdo and the initial edge of scl k rafters y pr goes active. if this bit is set fmr1.imod must be set also and bit rc0.0 must be cleared. rbs1...0? receive buffer size 00? buffer size : 2 frames 01? buffer size : 1 frame 10? buffer size : 9 2bits 11? bypass of receive elastic store 70 sic1 srsc rbs1 rbs0 s x sc x bs1 x bs0 (3c) 0t10 ? 12 t 1022 ? 1t11 ? 13 t 1023 ?
peb 2255 falc-lh v1.3 e1 registers data sheet 222 2000-07 s x sc? select transmit system clock 0? expected frequency on pin scl kx : 8 .1 9 2mhz calculation of delay time t (scl kx cycles) depends on the value x of the ?transmit counter offset? register x c1/0 and of the programming of x c1. x cos: delay t is an even number in the range of 0 to 1022: x cos = 0: x = 498 ? t/2 if x= 1010 ? t/2 if delay t is an odd number in the range of 1 to 1023: x cos = 1: x = 498 ? (t ? 1)/2 if x= 1010 ? (t ? 1)/2 if 1? expected frequency on pin scl kx :2.0 48 mhz calculation of delay time t (scl kx cycles) depends on the value x of the ?transmit counter offset? register x c1/0: t = (507 ? x/2) mod 256 delay time t = time between beginning of time slot 0 at x di and the initial edge of scl kx after s y p x goes active. if this bit is set fmr1.imod must be set also and bit x c0.0 must be cleared. x bs1...0? transmit buffer size 00? by-pass of transmit elastic store 01? buffer size : 1 frame 10? buffer size : 2 frames 11? buffer size : 9 2bits 0t 99 6 ? 9 98 t 1022 ? 1t 99 7 ? 9 99 t 1023 ?
peb 2255 falc-lh v1.3 e1 registers data sheet 223 2000-07 system interface control 2 (read/write) value after reset: 00 h ffs ? force freeze signaling setting this bit disables updating of the receive signaling buffer and current signaling information is frozen. after resetting this bit and receiving a complete superframe updating of the signaling buffer is started again. the freeze signaling status could be also automatically generated by detecting the loss of signal alarm or a loss of cas frame alignment or a receive slip (only if external register access via rsig is enabled). this automatic freeze signaling function is logically ored with this bit. the current internal freeze signaling status is available in register sis.sfs. ssf ? serial signaling format only applicable if pin function r/ x sig is selected. 0? bits 1... 4 in all time slots except time slots 0 + 16 are cleared. 1? bits 1... 4 in all time slots except time slots 0 + 16 are set high. srfso? select receive frame sync output 0? pin s y pr : input 1? pin s y pr : output setting this bit disables the timeslot assigner. with register rc1/0 the receive frame marker could be activated during any bit position of the current frame. this marker is active high for 2.0 48 mhz cycle and is clocked off with the falling edge of scl k r or rcl k if the receive elastic store is bypassed. if no s y pr has been activated since reset or software reset cmdr.res the outputs of the receive system interface assume an arbitrary alignment. calculation of the value x of the ?receive counter offset? register rc1/0 depends on scl k r and on the bit position bp which should be marked: x= (2 + 2bp) mod 512 ,forscl k r = 2.0 48 mhz 70 sic2 ffs ssf srfso (3d)
peb 2255 falc-lh v1.3 e1 registers data sheet 22 4 2000-07 line interface mode 3 (read/write) value after reset: 00 h csc? configure system clock cl k 16m/cl k 12m 0? dejittered x tal1 or x tal3 clock is output on cl k 16m/ cl k 12m. 1? buffered x tal1 or x tal3 clock is output on cl k 16m/ cl k 12m. esy? external synchronization of dco- x together with bit loop.spn the functionality of pin 8 0 is defined: programming of loop.spn and lim3.es y and the corresponding pin function is shown below. spn/es y : 00? function of pin 8 0 x sig: if sic3.ttrf = 1, transmit data from the system interface. no input function defined for sic3.ttrf = 0. 01? function of pin 8 0s y nc2: external synchronization input for the dco- x circuitry. 10? function of pin 8 0 roid: receive optical interface data. 11? function of pin 8 0 x sig: transmit signaling input from the transmit system interface. system interface control 3 (read/write) value after reset: 00 h ttrf? ttr register function setting this bit the function of the ttr1... 4 registers are changed. a one in each ttr register forces the x sigm marker high for the respective time slot and controls sampling of the time slots provided on pin x sig. x sig is selected by loop.spn = 0 and lim3.es y= 0. 70 lim3 csc es y (3e) 70 sic3 ttrf daf ( 4 0)
peb 2255 falc-lh v1.3 e1 registers data sheet 225 2000-07 daf? disable automatic freeze valid only if serial signaling access is enabled. 0? signaling is automatically frozen if one of the following alarms occurred: loss of signal (frs0.los), loss of cas frame alignment (frs1.ts16lfa) or receive slips (isr3.rsp/n). 1? automatic freezing of signaling data is disabled. u pdating of the signaling buffer is also done if one of the above described alarm conditions is active. however, updating of the signaling buffer is stopped if sic2.ffs is set. disable error counter (write) value after reset: 00 h dcec3? disable crc error counter 3 dcec2? disable crc error counter 2 dcec1? disable crc error counter debc ? disable errored block counter dcvc? disable code violation counter dfec? disable framing error counter these bits are only valid if fmr1.ecm is cleared. they have to be set before reading the error counters. they are reset automatically if the corresponding error counter high byte has been read. with the rising edge of these bits the error counters are latched and then cleared. 70 dec dcec3 dcec2 dcec1 debc dcvc dfec (60)
peb 2255 falc-lh v1.3 e1 registers data sheet 226 2000-07 transmit cas registers (write) value after reset: not defined transmit cas register 1...16 the transmit cas register access is enabled by setting bit x sp.casen = 1. each register except x s1 contains the cas bits for two time slots. with the transmit multiframe begin isr1. x mb the contents of these registers is copied into a shadow register. the contents is sent out subsequently in the time slots 16 of the outgoing data stream. note: if isr1.xmb is not used and the write access to these registers is done exact in that moment when this interrupt is generated, data may be lost. x s1.7 is sent out first and x s16.0 is sent last. the transmit multiframe begin interrupt ( x mb) requests that these registers should be serviced. if requests for new information are ignored, current contents is repeated. x s1 has to be programmed with the multiframe pattern. this pattern must always stay low, otherwise the remote end loses its synchronization. with setting the y -bit a remote alarm is transmitted to the far end. the y -bit is logically ored with bit ccr1. x ts16ra. the x bits (spare bits) should be set if they are not used. 70 x s1 0000 xyxx (70) x s2 a1 b1 c1 d1 a16 b16 c16 d16 (71) x s3 a2 b2 c2 d2 a17 b17 c17 d17 (72) x s 4 a3 b3 c3 d3 a1 8 b1 8 c1 8 d1 8 (73) x s5 a 4 b 4 c 4 d 4 a1 9 b1 9 c1 9 d1 9 (7 4 ) x s6 a5 b5 c5 d5 a20 b20 c20 d20 (75) x s7 a6 b6 c6 d6 a21 b21 c21 d21 (76) x s 8 a7 b7 c7 d7 a22 b22 c22 d22 (77) x s 9 a 8 b 8 c 8 d 8 a23 b23 c23 d23 (7 8 ) x s10 a 9 b 9 c 9 d 9 a2 4 b2 4 c2 4 d2 4 (7 9 ) x s11 a10 b10 c10 d10 a25 b25 c25 d25 (7a) x s12 a11 b11 c11 d11 a26 b26 c26 d26 (7b) x s13 a12 b12 c12 d12 a27 b27 c27 d27 (7c) x s1 4 a13 b13 c13 d13 a2 8 b2 8 c2 8 d2 8 (7d) x s15 a1 4 b1 4 c1 4 d1 4 a2 9 b2 9 c2 9 d2 9 (7e) x s16 a15 b15 c15 d15 a30 b30 c30 d30 (7f)
peb 2255 falc-lh v1.3 e1 registers data sheet 227 2000-07 if access to these registers is done without control of the interrupt isr1. x mb the registers should be written twice to avoid an internal data transfer error. note: a software reset (cmdr.xres) resets these registers.
peb 2255 falc-lh v1.3 e1 registers data sheet 22 8 2000-07 9.3 e1 status register addresses table 52 e1 status register address arrangement address register type comment page 00 rfifo r receive fifo 230 01 rfifo r receive fifo 230 4 b res r receive equalizer status 230 4 c frs0 r framer receive status 0 231 4 d frs1 r framer receive status 1 234 4 e rsw r receive service word 236 4 f rsp r receive spare bits 236 50 fecl r framing error counter low 238 51 fech r framing error counter high 238 52 cvcl r code violation counter low 239 53 cvch r code violation counter high 239 5 4 cec1l r crc error counter 1 low 240 55 cec1h r crc error counter 1 high 240 56 ebcl r e-bit error counter low 241 57 ebch r e-bit error counter high 241 5 8 cec2l r crc error counter 2 low 242 5 9 cec2h r crc error counter 2 high 242 5a cec3l r crc error counter 3 low 243 5b cec3h r crc error counter 3 high 243 5c rsa 4 r receive sa 4 bit register 244 5d rsa5 r receive sa5 bit register 244 5e rsa6 r receive sa6 bit register 244 5f rsa7 r receive sa7 bit register 244 60 rsa 8 r receive sa 8 bit register 244 61 rsa6s r receive sa6 bit status register 245 6 4 sis r signaling status register 246 65 rsis r receive signaling status register 247 66 rbcl r receive byte control low 248 67 rbch r receive byte control high 249
peb 2255 falc-lh v1.3 e1 registers data sheet 22 9 2000-07 6 8 isr0 r interrupt status register 0 249 6 9 isr1 r interrupt status register 1 251 6a isr2 r interrupt status register 2 253 6b isr3 r interrupt status register 3 254 6c isr5 r interrupt status register 5 256 6e gis r global interrupt status 256 6f vstr r version status 256 70 rs1 r receive cas register 1 257 71 rs2 r receive cas register 2 257 72 rs3 r receive cas register 3 257 73 rs 4 r receive cas register 4 257 7 4 rs5 r receive cas register 5 257 75 rs6 r receive cas register 6 257 76 rs7 r receive cas register 7 257 77 rs 8 r receive cas register 8 257 7 8 rs 9 r receive cas register 9 257 7 9 rs10 r receive cas register 10 257 7a rs11 r receive cas register 11 257 7b rs12 r receive cas register 12 257 7c rs13 r receive cas register 13 257 7d rs1 4 r receive cas register 1 4 257 7e rs15 r receive cas register 15 257 7f rs16 r receive cas register 16 257 table 52 e1 status register address arrangement (cont?d) address register type comment page
peb 2255 falc-lh v1.3 e1 registers data sheet 230 2000-07 9.4 detailed description of e1 status registers receive fifo (read) reading data from rfifo can be done in an 8 -bit (byte) or 16-bit (word) access depending on the selected bus interface mode. the lsb is received first from the serial interface. the size of the accessible part of rfifo is determined by programming the bits ccr1.rft 1 ? 0 (rfifo threshold level). it can be reduced from 32 bytes (reset value) down to 2 bytes (four values: 32, 16, 4 ,2bytes). data transfer u p to 32 bytes/16 words of received data can be read from the rfifo following an rpf or an rme interrupt. rpf interrupt: a fixed number of bytes/words to be read (32, 16, 4 ,2bytes).the message is not yet complete. rme interrupt: the message is completely received. the number of valid bytes is determined by reading the rbcl, rbch registers. rfifo is released by issuing the ?receive message complete? command (rmc). receive equalizer status (read) ev1?0... equalizer status valid these bits informs the user about the current state of the receive equalization network. only valid if lim1.e q on is set. 00? equalizer status not valid, still adapting 01? equalizer status valid 10? equalizer status not valid 11? equalizer status valid but high noise floor 70 rfifo rf7 rf0 (00/01) 70 res ev1 ev0 res 4 res3 res2 res1 res0 ( 4 b)
peb 2255 falc-lh v1.3 e1 registers data sheet 231 2000-07 res4?0... receive equalizer status the current line attenuation status in steps of about 1.7 db are displayed in these bits. only valid if bits ev1...0 = 01 and lim1.e q on = 1. accuracy: + /- 2 digit, based on temperature influence and noise amplitude variations. 00000? attenuation (0 db) ... 11001? max. attenuation framer receive status register 0 (read) los? loss of signal detection : this bit is set when the incoming signal has ?no transitions? (analog interface) or logical zeros (digital interface) in a time interval of t consecutive pulses, where t is programmable by register pcd. total account of consecutive pulses: 16 < t <4 0 9 6. analog interface: the receive signal level where ?no transition? is declared is defined by the programmed value of lim1.ril2...0 (short haul mode only, lim1.e q on = 0). recovery : analog interface: the bit is reset in short haul mode when the incoming signal has transitions with signal levels greater than the programmed receive input level (lim1.ril2...0 ; short haul mode only) for at least m pulse periods defined by register pcr in the pcd time interval. digital interface: the bit is reset when the incoming data stream contains at least m ones defined by register pcr in the pcd time interval. with the rising edge of this bit an interrupt status bit (isr2.los) is set. for additional recovery conditions see register lim2.los2...1. the bit is also set during alarm simulation and reset if fmr0.sim is cleared and no alarm condition exists. 70 frs0 los ais lfa rra a ux pnmflmfa ( 4 c)
peb 2255 falc-lh v1.3 e1 registers data sheet 232 2000-07 ais? alarm indication signal the function of this bit is determined by fmr0.alm. fmr0.alm = 0: this bit is set when two or less zeros in the received bit stream are detected in a time interval of 250 s and the falc ? -lh is in asynchronous state (frs0.lfa = 1). the bit is reset when no alarm condition is detected (according to etsi standard). fmr0.alm = 1: this bit is set when the incoming signal has two or less z eros in each of two consecutive double frame period (512 bits). this bit is cleared when each of two consecutive doubleframe periods contain three or more zeros or when the frame alignment signal fas has been found. (according to it u -t g.775 standard) the bit is also set during alarm simulation and reset if fmr0.sim is cleared and no alarm condition exists. with the rising edge of this bit an interrupt status bit (isr2.ais) is set. lfa? loss of frame alignment this bit is set after detecting 3 or 4 consecutive incorrect fas words or 3 or 4 consecutive incorrect service words (can be disabled). with the rising edge of this bit an interrupt status bit (isr2.lfa) is set. the specification of the loss of sync conditions is done via bits rc1.swd and rc1.as y4 . after loss of synchronization, the frame aligner resynchronizes automatically. the following conditions have to be detected to regain synchronous state: ? the presence of the correct fas word in frame n. ? the presence of the correct service word (bit 2 = 1) in frame n + 1. ? for a second time the presence of a correct fas word in frame n + 2. the bit is cleared when synchronization has been regained (directly after the second correct fas word of the procedure described above has been received). if the crc-multiframe structure is enabled by setting bit fmr2.rfs1, multiframe alignment is assumed to be lost if pulse-frame synchronization has been lost. the resynchronization procedure for multiframe alignment starts after the bit frs0.lfa has been cleared.
peb 2255 falc-lh v1.3 e1 registers data sheet 233 2000-07 multiframe alignment has been regained if two consecutive crc- multiframes have been received without a framing error (refer to frs0.lmfa). the bit is set during alarm simulation and reset if fmr0.sim is cleared and no alarm condition exists. if bit frs0.lfa is cleared a loss of frame alignment recovery interrupt status isr2.far is generated. rra? receive remote alarm set if bit 3 of the received service word is set. an alarm interrupt status isr2.ra can be generated if the alarm condition is detected. frs0.rra is cleared when no alarm is detected. at the same time a remote alarm recovery interrupt status isr2.rar is generated. the bit rsw.rra has the same function. both status and interrupt status bits are set during alarm simulation. au x p? auxiliary pattern indication this bit is set when 25 4 or more ?10? are received in a time interval of 250 s and the frame alignment is lost frs0.lfa = 1. an interrupt status isr3.api is generated if this bit is set. the bit is reset when no auxiliary pattern condition is detected. the bit is also set during alarm simulation and reset if fmr0.sim is cleared and no alarm condition exists. nmf? no multiframe alignment found this bit is only valid if the crc 4 interworking is selected (fmr2.rfs1/0 = 11). set if the multiframe pattern could not be detected in a time interval of 4 00 ms after the framer has reached the doubleframe synchronous state. the receiver is then automatically switched to doubleframe format. this bit is reset if the basic framing has been lost.
peb 2255 falc-lh v1.3 e1 registers data sheet 23 4 2000-07 lmfa? loss of multiframe alignment not used in doubleframe format (fmr2.rfs1 = 0). in this case, lmfa is set. in crc-multiframe mode (fmr2.rfs1 = 1), this bit is set ? if force resynchronization is initiated by setting bit fmr0.frs, or ? if multiframe force resynchronization is initiated by setting bit fmr1.mfcs, or ? if pulseframe alignment has been lost (frs0.lfa). it is reset if two crc-multiframes have been received at an interval of n 2ms(n = 1, 2, 3?) without a framing error. if bit frs0.lmfa is cleared a loss of multiframe alignment recovery interrupt status isr2.mfar is generated. framer receive status register 1 (read) ts16ra? receive timeslot 16 remote alarm this bit contains the actual information of the received remote alarm bit rs1.2 in time slot 16. setting and resetting of this bit causes an interrupt status change isr3.ra16. ts16los? receive timeslot 16 loss of signal this bit is set if the incoming ts16 data stream contains always zeros for at least 16 contiguously received time slots. a one in a time slot 16 resets this bit. ts16ais? receive timeslot 16 alarm indication signal the detection of the alarm indication signal in timeslot 16 is according to it u -t g.775. this bit is set if the incoming ts16 contains less than 4 zeros in each of two consecutive ts16 multiframe periods. this bit is cleared if two consecutive received cas multiframe periods contains more than 3 zeros or the multiframe pattern was found in each of them. this bit is cleared if ts0 synchronization is lost. 70 frs1 ts16ra ts16los ts16ais ts16lfa x ls x lo ( 4 d)
peb 2255 falc-lh v1.3 e1 registers data sheet 235 2000-07 ts16lfa? receive timeslot 16 loss of multiframe alignment 0? the cas controller is in synchronous state after frame alignment is accomplished. 1? this bit is set if the framing pattern ?0000? in 2 consecutive cas multiframes were not found or in all ts16 of the preceding multiframe all bits were reset. an interrupt isr3.lmfa16 is generated. x ls? transmit line short significant only if the ternary line interface is selected by lim1.drs = 0. 0? normal operation. no short is detected. 1? the x l1 and x l2 are shortened for at least 32 pulses. as a reaction of the short the pins x l1 and x l2 are automatically forced into a high impedance state if bit x pm2.da x lt is reset. after 32 consecutive pulse periods the outputs x l1/2 are activated again and the internal transmit current limiter is checked. if a short between x l1/2 is still further active the outputs x l1/2 are in high impedance state again. when the short disappears pins x l1/2 are activated automatically and this bit is reset. with any change of this bit an interrupt isr1. x lsc is generated. in case of x pm2. x lt is set this bit is frozen. x lo? transmit line open 0? normal operation 1? this bit is set if at least 32 consecutive zeros were sent via pins x l1/ x l2 or x dop/ x don. this bit is reset with the first transmitted pulse. with the rising edge of this bit an interrupt isr1. x lsc is set. in case of x pm2. x lt is set this bit is frozen.
peb 2255 falc-lh v1.3 e1 registers data sheet 236 2000-07 receive service word pulseframe (read) rsi? receive spare bit for international use first bit of the received service word. it is fixed to one if crc- multiframe mode is enabled. rra? receive remote alarm equivalent to bit frs0.rra. ry0?ry4? receive spare bits for national use (y-bits, s n -bits, s a -bits) receive spare bits/additional status (read) si1?si2? submultiframe error indication 1, 2 not valid if doubleframe format is enabled. in this case, both bits are set. when using crc-multiframe format these bits are set to 0? if multiframe alignment has been lost, or if the last multiframe has been received with crc error(s). si1 flags a crc error in last sub-multiframe 1, si2 flags a crc error in last sub-multiframe 2. 1? if at multiframe synchronous state last assigned sub-multiframe has been received without a crc error. both flags are updated with beginning of every received crc multiframe. if automatic transmission of sub-multiframe status is enabled by setting bit x sp.a x s, above status information is inserted automatically in s i -bit position of every outgoing crc multiframe (under the condition that time slot 0 transparent modes are both disabled): si1 s i -bit of frame 13, si2 s i -bit of frame 15. 70 rsw rsi rra r y 0r y 1r y 2r y 3r y4 ( 4 e) 70 rsp si1 si2 llbdd llbad rsif rs13 rs15 ( 4 f)
peb 2255 falc-lh v1.3 e1 registers data sheet 237 2000-07 llbdd? line loop back deactivation signal detected this bit is set in case the llb deactivate signal is detected and then received over a period of more than 25 ms with a bit error rate less than 1/100. the bit remains set as long as the bit error rate does not exceed 1/100. if framing is aligned, the timeslot 0 is not taken into account for the error rate calculation. any change of this bit causes a llbsc interrupt. llbad? line loop back activation signal detected depending on bit lcr1.eprm the source of this status bit changed. lcr1.eprm = 0: this bit is set in case the llb activate signal is detected and then received over a period of more than 25 ms with a bit error rate less than 1/100. the bit remains set as long as the bit error rate does not exceed 1/100. if framing is aligned, the timeslot 0 is not taken into account for the error rate calculation. any change of this bit causes a llbsc interrupt. prbs status lcr1.eprm = 1: the current status of the prbs synchronizer is indicated in this bit. it is set high if the synchronous state is reached even in the presence of a ber 1/10. a data stream containing all zeros with/without framing bits is also a valid pseudo random bit sequence. the same applies to an all ones data stream. rsif? receive spare bit for international use (fas word) first bit in fas-word. u sed only in doubleframe format, otherwise fixed to ?1?. rs13? receive spare bit (frame 13, crc multiframe) first bit in service word of frame 13. significant only in crc- multiframe format, otherwise fixed to ?0?. this bit is updated with beginning of every received crc multiframe. rs15? receive spare bit (frame 15, crc multiframe) first bit in service word of frame 15. significant only in crc- multiframe format, otherwise fixed to ?0?. this bit is updated with beginning of every received crc multiframe.
peb 2255 falc-lh v1.3 e1 registers data sheet 23 8 2000-07 framing error counter (read) fe15?0? framing errors this 16-bit counter is incremented when a fas word has been received with an error. framing errors are counted during basic frame synchronous state only (but even if multiframe synchronous state is not reached yet). during alarm simulation, the counter is incremented every 250 sup to its saturation. the error counter doesn?t roll over. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dfec has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.dfec is reset automatically with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. 70 fecl fe7 fe0 (50) 70 fech fe15 fe 8 (51)
peb 2255 falc-lh v1.3 e1 registers data sheet 23 9 2000-07 code violation counter (read) cv15?0? code violations no function if nr z code has been enabled. if the hdb3 or the cmi code is selected, the 16-bit counter is incremented when violations of the hdb3 code are detected. the error detection mode is determined by programming the bit fmr0.e x td. if simple ami coding is enabled (fmr0.rc0/1 = 10) all bipolar violations are counted. the error counter doesn?t roll over. during alarm simulation, the counter is incremented every four bits received up to its saturation. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcvc has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.dcvc is reset automatically with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. 70 cvcl cv7 cv0 (52) 70 cvch cv15 cv 8 (53)
peb 2255 falc-lh v1.3 e1 registers data sheet 2 4 0 2000-07 crcerrorcounter1(read) cr15?0? crc errors no function if doubleframe format is selected. in crc-multiframe mode, the 16-bit counter is incremented when a crc-submultiframe has been received with a crc error. crc errors don?t count during asynchronous state. the error counter doesn?t roll over. during alarm simulation, the counter is incremented once per submultiframe up to its saturation. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcec1 has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.dcec1 is reset automatically with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. 70 cec1l cr7 cr0 (5 4 ) 70 cec1h cr15 cr 8 (55)
peb 2255 falc-lh v1.3 e1 registers data sheet 2 4 1 2000-07 e bit error counter (read) eb15?0? e-bit errors if doubleframe format is selected, febeh/l has no function. if crc- multiframe mode is enabled, febeh/l works as submultiframe error indication counter (16 bits) which counts zeros in s i -bit position of frame 13 and 15 of every received crc multiframe. the error counter doesn?t roll over. during alarm simulation, the counter is incremented once per submultiframe up to its saturation. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.debc has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.debc is reset automatically with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. 70 ebcl eb7 eb0 (56) 70 ebch eb15 eb 8 (57)
peb 2255 falc-lh v1.3 e1 registers data sheet 2 4 2 2000-07 crcerrorcounter2(read) cc15?0? crc error counter (reported from te via sa6 -bit) depending on bit lcr1.eprm the error counter increment is selected: lcr1.eprm = 0: if doubleframe format is selected, cec2h/l has no function. if crc- multiframe mode is enabled, cec2h/l works as sa6 bit error indication counter (16 bits) which counts the sa6 bit sequence 0001 and 0011in every received crc submultiframe. incrementing the counter is only possible in the multiframe synchronous state frs0.lmfa = 0. sa6 bit sequence: sa61, sa62, sa63, sa6 4= 0001 or 0011 where sa61isreceivedinframe1or 9 in every multiframe. pseudo random bit sequence error counter lcr1.eprm = 1: this 16-bit counter is incremented with every received prbs bit error in the prbs synchronous state rsp.llbad = 1. the error counter doesn?t roll over. during alarm simulation, the counter is incremented once per submultiframe up to its saturation. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcec2 has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.dcec2 is reset automatically with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. 70 cec2l cc7 cc0 (5 8 ) 70 cec2h cc15 cc 8 (5 9 )
peb 2255 falc-lh v1.3 e1 registers data sheet 2 4 3 2000-07 crcerrorcounter3(read) ce15?0? crc error counter (detected at t ref. point via sa6 -bit) if doubleframe format is selected, cec3h/l has no function. if crc- multiframe mode is enabled, cec3h/l works as sa6 bit error indication counter (16 bits) which counts the sa6 bit sequence 0010 and 0011in every received crc submultiframe. incrementing the counter is only possible in the multiframe synchronous state frs0.lmfa = 0. sa6 bit sequence: sa6 1 , sa6 2 , sa6 3 , sa6 4 = 0010 or 0011 where sa6 1 is received in frame 1 or 9 in every multiframe. clearing and updating the counter is done according to bit fmr1.ecm. during alarm simulation, the counter is incremented once per multiframe up to its saturation. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcec3 has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.dcec3 is reset automatically with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. 70 cec3l ce7 ce0 (5a) 70 cec3h ce15 ce 8 (5b)
peb 2255 falc-lh v1.3 e1 registers data sheet 2 44 2000-07 receive sa4-bit register (read) rs47?40? receive sa4-bit data (y-bits) rs57?50? receive sa5-bit data rs67?60? receive sa6-bit data rs77?70? receive sa7-bit data rs87?80? receive sa8-bit data this register contains the information of the eight sax bits (x =4 ... 8 ) of the previously received crc multiframe. these registers are updated with every multiframe begin interrupt isr0.rmb. rs 4 0isreceivedinbit-slot 4 of every service word in frame 1, rs 4 7 in frame 15 rs50 is received in bit-slot 5, time slot 0, frame 1, rs57 in frame 15 rs60 is received in bit-slot 6, time slot 0, frame 1, rs67 in frame 15 rs70 is received in bit-slot 7, time slot 0, frame 1, rs77 in frame 15 rs 8 0isreceivedinbit-slot 8 ,timeslot0,frame1,rs 8 7inframe15 valid if crc multiframe format is enabled by setting bits fmr2.rfs1 = 1orfmr2.rfs1/0 = 01 (doubleframe format). 70 rsa 4 rs 4 7rs 4 0 (5c) rsa5 rs57 rs50 (5d) rsa6 rs67 rs60 (5e) rsa7 rs77 rs70 (5f) rsa 8 rs 8 7rs 8 0 (60)
peb 2255 falc-lh v1.3 e1 registers data sheet 2 4 5 2000-07 receive sa6-bit status (read) four consecutive received sa6-bits are checked on the by ets 300233 defined sa6-bit combinations. the falc ? -lh detects the following ?fixed? sa6-bit combinations: sa61,sa62,sa63,sa6 4= 1000 ; 1010 ; 1100 ; 1110 ; 1111. all other possible 4 bit combinations are grouped to status ? x ?. a valid sa6-bit combination must occur three times in a row. the corresponding status bit in this register is set. even if the detected status is active for a short time the status bit remains active until this register is read. reading the register resets all pending status information. with any change of state of the sa6-bit combinations an interrupt status isr0.sa6sc is generated. during the basic frame asynchronous state updating of this register and interrupt status isr0.sa6sc is disabled. in multiframe format the detection of the sa6-bit combinations can be done either synchronous or asynchronous to the submultiframe (fmr3.sa6s y ). in synchronous detection mode updating of register rsa6s is done in the multiframe synchronous state (frs0.lmfa = 0). in asynchronous state detection mode updating is independent of the multiframe synchronous state. s _x ? receive s a 6-bit status _x if none of the fixed sa6-bit combinations are detected this bit is set. s _ f? receive s a 6-bit status: ?1111? receive sa6-bit status ?1111? is detected for three times in a row in the sa6-bit positions. s _ e? receive s a 6-bit status: ?1110? receive sa6-bit status ?1110? is detected for three times in a row in the sa6-bit positions. s _ c? receive s a 6-bit status: ?1100? receive sa6-bit status ?1100? is detected for three times in a row in the sa6-bit positions. 70 rsa6s s_ x s_f s_e s_c s_a s_ 8 (61)
peb 2255 falc-lh v1.3 e1 registers data sheet 2 4 6 2000-07 s _ a? receive sa6-bit status: ?1010? receive sa6-bit status ?1010? is detected for three times in a row in the sa6-bit positions. s _ 8? receive sa6-bit status: ?1000? receive sa6-bit status ?1000? is detected for three times in a row in the sa6-bit positions. signaling status register (read) x dov? transmit data overflow more than 32 bytes have been written to the x fifo. this bit is reset by: ? a transmitter reset command x res ? or when all bytes in the accessible half of the x fifo have been moved in the inaccessible half. x fw? transmit fifo write enable datacanbewrittentothe x fifo. x rep? transmission repeat status indication of cmdr. x rep. rli? receive line inactive neither flags as interframe time fill nor frames are received via the signaling timeslot. cec? command executing 0? no command is currently executed, the cmdr register can be written to. 1? a command (written previously to cmdr) is currently executed, no further command can be temporarily written in cmdr register. note: cec is active at most 2.5 periods of the current system data rate. sfs? status freeze signaling 0? freeze signaling status inactive. 1? freeze signaling status active 70 sis x dov x fw x rep rli cec sfs (6 4 )
peb 2255 falc-lh v1.3 e1 registers data sheet 2 4 7 2000-07 receive signaling status register (read) rsis relates to the last received hdlc frame ; it is copied into rfifo when end-of-frame is recognized (last byte of each stored frame). vfr? valid frame determines whether a valid frame has been received. 1? valid hdlc frame 0? invalid hdlc frame an invalid frame is either ? a frame which is not an integer number of 8 bits (n 8 bits) in length (e.g.25bits),or ? a frame which is too short taking into account the operation mode selected via mode (mds2...0) and the selection of receive crc on/off (ccr3.rcrc) as follows: mds2...0 = 011 (16 bit address), rcrc = 0: 4 bytes ; rcrc = 1:3- 4 bytes mds2...0 = 010 ( 8 bit address), rcrc = 0:3bytes ; rcrc = 1:2-3bytes note: shorter frames are not reported. rdo? receive data overflow a rfifo data overflow has occurred during reception of the frame. additionally, an interrupt can be generated (refer to isr1.rdo/ imr1.rdo). crc16? crc16 compare/check 0? crc check failed ; received frame contains errors. 1? crc check o.k. ; received frame is error-free. rab? receive message aborted the received frame was aborted from the transmitting station. according to the hdlc protocol, this frame must be discarded by the receiver station. 70 rsis vfr rdo crc16 rab ha1 ha0 la (65)
peb 2255 falc-lh v1.3 e1 registers data sheet 2 48 2000-07 ha1...0? high byte address compare significant only if 2-byte address mode has been selected. in operating modes which provide high byte address recognition, the falc ? -lh compares the high byte of a 2-byte address with the contents of two individually programmable registers (rah1, rah2) and the fixed values fe h and fc h (broadcast address). dependent on the result of this comparison, the following bit combinations are possible: 00? rah2 has been recognized 01? broadcast address has been recognized 10? rah1 has been recognized c/r = 0(bit1) 11? rah1 has been recognized c/r = 1(bit1) note: if rah1, rah2 contain identical values, a match is indicated by ? 10 ? or ? 11 ? . la? low byte address compare significant in hdlc modes only. the low byte address of a 2-byte address field, or the single address byte of a 1-byte address field is compared with two registers. (ral1, ral2). 0? ral2 has been recognized 1? ral1 has been recognized receive byte count low (read) together with rbch (bits rbc11... 8 ) indicates the length of a received frame (1? 4 0 9 5bytes).bitsrbc 4 -0 indicate the number of valid bytes currently in rfifo. these registers must be read by the cp u following an rme interrupt. 70 rbcl rbc7 rbc0 (66)
peb 2255 falc-lh v1.3 e1 registers data sheet 2 49 2000-07 received byte count high (read) ov? counter overflow more than 4 0 9 5 bytes received. rbc11...8? receive byte count (most significant bits) together with rbcl (bits rbc7?rbc0) indicate the length of the received frame. interrupt status register 0 (read) value after reset: 00 h all bits are reset when isr0 is read. if bit ipc.vis is set, interrupt statuses in isr0 may be flagged although they are masked via register imr0. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. rme? receive message end one complete message of length less than 32 bytes, or the last part of a frame at least 32 bytes long is stored in the receive fifo, including the status byte. the complete message length can be determined reading the rbch, rbcl registers, the number of bytes currently stored in rfifo is given by rbc 4 ...0. additional information is available in the rsis register. 70 rbch ov rbc11 rbc10 rbc 9 rbc 8 (67) 70 isr0 rme rfs t 8 ms rmb casc crc 4 sa6sc rpf (6 8 )
peb 2255 falc-lh v1.3 e1 registers data sheet 250 2000-07 rfs? receive frame start this is an early receiver interrupt activated after the start of a valid frame has been detected, i.e. after an address match (in operation modes providing address recognition), or after the opening flag (transparent mode 0) is detected, delayed by two bytes. after an rfs interrupt, the contents of rsis-bits 3...1 is valid and can be read by the cp u . t8ms? receive time out 8 msec only active if multiframing is enabled. the framer has found the doubleframing (basic framing) frs0.lfa = 0 and is searching for the multiframing. this interrupt is set to indicate that no multiframing could be found within a time window of 8 msec. in multiframe synchronous state this interrupt is not generated. refer also to floating multiframe alignment window. rmb? receive multiframe begin this bit is set with the beginning of a received crc multiframe related to the internal receive line timing. in crc multiframe format fmr2.rfs1 = 1 or in doubleframe format fmr2.rfs1...0 = 01 this interrupt occurs every 2 msec. if fmr2.rfs1...0 = 00 this interrupt is generated every doubleframe (512 bits). casc? received cas information changed this bit is set with the updating of a received cas multiframe information in the registers rs1...16. if the last received cas information is different to the previous received one, this interrupt is generated after update has been completed. this interrupt occurs only in ts0 and ts16 synchronous state. the registers rs1...16 should be read within the next 2 ms otherwise the contents may be lost. crc4? receive crc4 error 0... no crc 4 error occurs. 1... the crc 4 check of a received submultiframe failed. sa6sc? receive sa6-bit status changed with every change of state of the received sa6-bit combinations this interrupt is set.
peb 2255 falc-lh v1.3 e1 registers data sheet 251 2000-07 rpf? receive pool full 32 bytes of a frame have arrived in the receive fifo. the frame is not yet completely received. interrupt status register 1 (read) all bits are reset when isr1 is read. if bit ipc.vis is set, interrupt statuses in isr1 may be flagged although they are masked via register imr1. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. llbsc? line loop back status change depending on bit lcr1.eprm the source of this interrupt status changed: lcr1.eprm = 0: this bit is set, if the llb activate signal or the llb deactivate signal, respectively is detected over a period of 25 ms with a bit error rate less than 1/100. the llbsc bit is also set, if the current detection status is left, i.e., if the bit error rate exceeds 1/100. the actual detection status can be read from the rsp.llbad and rsp.llbdd, respectively. prbs status change lcr1.eprm = 1: with any change of state of the prbs synchronizer this bit is set. the current status of the prbs synchronizer is indicated in rsp.llbad. rdo? receive data overflow this interrupt status indicates that the cp u did not respond fast enough to an rpf or rme interrupt and that data in rfifo has been lost. even when this interrupt status is generated, the frame continues to be received when space in the rfifo is available again. note: whereas the bit rsis.rdo in the frame status byte indicates whether an overflow occurred when receiving the frame currently accessed in the rfifo, the isr1.rdo interrupt status is generated as soon as an overflow occurs and does not necessarily pertain to the frame currently accessed by the processor. 70 isr1 llbsc rdo alls x d ux mb x lsc x pr (6 9 )
peb 2255 falc-lh v1.3 e1 registers data sheet 252 2000-07 alls? all sent this bit is set if the last bit of the current frame has been sent out completely and x fifo is empty. x du? transmit data underrun transmitted frame was terminated with an abort sequence because no data was available for transmission in x fifo and no x me was issued. note: transmitter and xfifo are reset and deactivated if this condition occurs. they are re-activated not before this interrupt status register has been read. thus, xdu should not be masked via register imr1. x mb? transmit multiframe begin this bit is set every 2 ms with the beginning of a multiframe transmission and is related to the internal transmit line interface timing. after setting this bit, registers x s1...16 are copied into the transmit shift registers. the registers x s1...16 are now ready for the next data and have to be updated ; otherwise the contents is retransmitted during the next multiframe. a wait time of 3 s has to be observed between reading of x mb = 1 and start of reprogramming x s1...16. x lsc? transmit line status change x lsc is set with the rising edge of the bit frs1. x lo or with any change of bit frs1. x ls. the actual status of the transmit line monitor can be read from the frs1. x ls and frs1. x lo. x pr? transmit pool ready a data block of up to 32 bytes can be written to the transmit fifo. x pr enables the fastest access to x fifo. it has to be used for transmission of long frames, back-to-back frames or frames with shared flags.
peb 2255 falc-lh v1.3 e1 registers data sheet 253 2000-07 interrupt status register 2 (read) all bits are reset when isr2 is read. if bit ipc.vis is set, interrupt statuses in isr2 may be flagged although they are masked via register imr2. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. far? frame alignment recovery the framer has reached doubleframe synchronization. set when bit fsr0.lfa is reset. it is set also after alarm simulation is finished and the receiver is still synchronous. lfa? loss of frame alignment the framer has lost synchronization and bit frs0.lfa is set. it is set during alarm simulation. mfar? multiframe alignment recovery set when the framer has found two crc-multiframes at an interval of n 2ms(n = 1, 2, 3, ?) without a framing error. at the same time bit frs0.lmfa is reset. it is set also after alarm simulation is finished and the receiver is still synchronous. only active if crc-multiframe format is selected. t400ms? receive time out 400 msec only active if multiframing is enabled. the framer has found the doubleframing (basic framing) frs0.lfa = 0 and is searching for the multiframing. this interrupt is set to indicate that no multiframing could be found within a time window of 4 00 ms after basic framing has been achieved. in multiframe synchronous state this interrupt is not generated. ais? alarm indication signal this bit is set when an alarm indication signal is detected and bit frs0.ais is set. it is set during alarm simulation. if ipc.sci is set high this interrupt status bit is set with every change of state of frs0.ais. 70 isr2 far lfa mfar t 4 00ms ais los rar ra (6a)
peb 2255 falc-lh v1.3 e1 registers data sheet 25 4 2000-07 los? loss of signal this bit is set when a loss of signal alarm is detected in the received bit stream and frs0.los is set. it is set during alarm simulation. if ipc.sci is set high this interrupt status bit is set with every change of state of frs0.los. rar? remote alarm recovery set if a remote alarm in ts0 is cleared and bit frs0.ra is reset. it is set also after alarm simulation is finished and no remote alarm is detected. ra? remote alarm set if a remote alarm in ts0 is detected and bit frs0.ra is set. it is set during alarm simulation. interrupt status register 3 (read) all bits are reset when isr3 is read. if bit ipc.vis is set, interrupt statuses in isr3 may be flagged although they are masked via register imr3. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. es? errored second this bit is set if at least one enabled interrupt source via imr 4 is set during the time interval of one second. interrupt sources of imr 4 register: lfa = loss of frame alignment detected (frs0.lfa) fer = framing error received cer = crc error received ais = alarm indication signal (frs0.ais) los = loss of signal (frs0.los) cve = code violation detected slip = receive slip positive/negative detected ebe = e-bit error detected (rsp.rs13/15) sec? second timer the internal one second timer has expired. the timer is derived from clock rcl k . 70 isr3 es sec lmfa16 ais16 ra16 api rsn rsp (6b)
peb 2255 falc-lh v1.3 e1 registers data sheet 255 2000-07 lmfa16? loss of multiframe alignment ts 16 multiframe alignment of timeslot 16 has been lost if two consecutive multiframe pattern are not detected or if in 16 consecutive timeslot 16 all bits are reset. if register ipc.sci is high this interrupt status bit is set with every change of state of frs1.ts16lfa. ais16? alarm indication signal ts 16 status change the alarm indication signal ais in timeslot 16 for the 6 4 kbit/s channel associated signaling is detected or cleared. a change in bit frs1.ts16ais sets this interrupt (this bit is set if the incoming ts 16 signal contains less than 4 zeros in each of two consecutive ts16- multiframe periods.). ra16? remote alarm ts 16 status change a change in the remote alarm bit in cas multiframe alignment word is detected. api? auxiliary pattern indication this bit is set if the auxiliary pattern is detected in the received bit stream and bit frs0.a ux pisset. if register ipc.sci is high this interrupt status bit is set with every change of state of frs0.a ux p. rsn? receive slip negative the frequency of the receive route clock is greater than the frequency of the receive system interface working clock based on 2.0 48 mhz. it is set during alarm simulation. in 2-frame buffer mode a frame is skipped. rsp? receive slip positive the frequency of the receive route clock is less than the frequency of the receive system interface working clock based on 2.0 48 mhz. it is set during alarm simulation. in 2-frame buffer mode a frame is repeated.
peb 2255 falc-lh v1.3 e1 registers data sheet 256 2000-07 interrupt status register 5 (read) all bits are reset when isr5 is read. if bit ipc.vis is set, interrupt statuses in isr 4 may be flagged although they are masked via register imr5. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. x sp? transmit slip positive the frequency of the transmit clock is less than the frequency of the transmit system interface working clock based on 2.0 48 mhz. in 2-frame buffer mode a frame is skipped. x sn? transmit slip negative the frequency of the transmit clock is greater than the frequency of the transmit system interface working clock based on 2.0 48 mhz. in 2-frame buffer mode a frame is repeated global interrupt status register (read) value after reset: 00 h this status register points to pending interrupts sourced by isr5 and isr3...isr0. version status register (read) vn7...0? version number of chip 10 h ?version 1.1 13 h ?version 1.3 70 isr5 x sp x sn (6c) 70 gis isr5 isr3 isr2 isr1 isr0 (6e) 70 vstr vn7 vn6 vn5 vn 4 vn3 vn2 vn1 vn0 (6f)
peb 2255 falc-lh v1.3 e1 registers data sheet 257 2000-07 receive cas registers (read) value after reset: not defined receive cas register 1...16 each register except rs1 contains the received cas bits for two time slots. the received cas multiframe is compared with the previously received one. if the contents changed a cas multiframe changed interrupt (isr0.casc) is generated and informs the user that a new multiframe has to be read within the next 2 ms. if requests for reading the rs1...16 register are ignored, the received data may be lost. rs1 contains frame 0 of the cas multiframe. msb is received first. 70 rs1 0000 xyx x (70) rs2 a1 b1 c1 d1 a16 b16 c16 d16 (71) rs3 a2 b2 c2 d2 a17 b17 c17 d17 (72) rs 4 a3 b3 c3 d3 a1 8 b1 8 c1 8 d1 8 (73) rs5 a 4 b 4 c 4 d 4 a1 9 b1 9 c1 9 d1 9 (7 4 ) rs6 a5 b5 c5 d5 a20 b20 c20 d20 (75) rs7 a6 b6 c6 d6 a21 b21 c21 d21 (76) rs 8 a7 b7 c7 d7 a22 b22 c22 d22 (77) rs 9 a 8 b 8 c 8 d 8 a23 b23 c23 d23 (7 8 ) rs10 a 9 b 9 c 9 d 9 a2 4 b2 4 c2 4 d2 4 (7 9 ) rs11 a10 b10 c10 d10 a25 b25 c25 d25 (7a) rs12 a11 b11 c11 d11 a26 b26 c26 d26 (7b) rs13 a12 b12 c12 d12 a27 b27 c27 d27 (7c) rs1 4 a13 b13 c13 d13 a2 8 b2 8 c2 8 d2 8 (7d) rs15 a1 4 b1 4 c1 4 d1 4 a2 9 b2 9 c2 9 d2 9 (7e) rs16 a15 b15 c15 d15 a30 b30 c30 d30 (7f)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 25 8 2000-07 10 t1/j1 registers 10.1 t1/j1 control register addresses table 53 t1/j1 control register address arrangement address register type comment page 00 x fifo w transmit fifo 261 01 x fifo w transmit fifo 261 02 cmdr w command register 261 03 mode r/w mode register 263 0 4 rah1 r/w receive address high 1 264 05 rah2 r/w receive address high 2 264 06 ral1 r/w receive address low 1 264 07 ral2 r/w receive address low 2 265 0 8 ipc r/w interrupt port configuration 265 0 9 ccr1 r/w common configuration register 1 266 0a ccr3 r/w common configuration register 3 268 0b pre r/w preamble register 269 0c rtr1 r/w receive timeslot register 1 270 0d rtr2 r/w receive timeslot register 2 270 0e rtr3 r/w receive timeslot register 3 270 0f rtr 4 r/w receive timeslot register 4 270 10 ttr1 r/w transmit timeslot register 1 271 11 ttr2 r/w transmit timeslot register 2 271 12 ttr3 r/w transmit timeslot register 3 271 13 ttr 4 r/w transmit timeslot register 4 271 1 4 imr0 r/w interrupt mask register 0 272 15 imr1 r/w interrupt mask register 1 272 16 imr2 r/w interrupt mask register 2 272 17 imr3 r/w interrupt mask register 3 272 1 8 imr 4 r/w interrupt mask register 4 272 1 9 imr5 r/w interrupt mask register 5 272 1a fmr0 r/w framer mode register 0 272
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 25 9 2000-07 1b fmr1 r/w framer mode register 1 274 1c fmr2 r/w framer mode register 2 276 1d loop r/w channel loop back register 278 1e fmr 4 r/w framer mode register 4 279 1f fmr5 r/w framer mode register 5 281 20 x c0 r/w transmit control 0 283 21 x c1 r/w transmit control 1 284 22 rc0 r/w receive control 0 284 23 rc1 r/w receive control 1 286 2 4x pm0 r/w transmit pulse mask 0 288 25 x pm1 r/w transmit pulse mask 1 288 26 x pm2 r/w transmit pulse mask 2 288 2 9 idle r/w idle channel code 289 2a x dl1 r/w transmit dl-bit register 1 290 2b x dl2 r/w transmit dl-bit register 2 290 2c x dl3 r/w transmit dl-bit register 3 290 2d ccb1 r/w clear channel register 1 290 2e ccb2 r/w clear channel register 2 290 2f ccb3 r/w clear channel register 3 290 30 icb1 r/w idle channel register 1 291 31 icb2 r/w idle channel register 2 291 32 icb3 r/w idle channel register 3 291 3 4 lim0 r/w line interface mode 0 291 35 lim1 r/w line interface mode 1 293 36 pcd r/w pulse count detection 294 37 pcr r/w pulse count recovery 295 3 8 lim2 r/w line interface register 2 295 3 9 lcr1 r/w loop code register 1 297 3a lcr2 r/w loop code register 2 299 3b lcr3 r/w loop code register 3 299 table 53 t1/j1 control register address arrangement (cont?d) address register type comment page
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 260 2000-07 after ?reset? all control registers except the x fifo and x s1...12 are initialized to defined values. u nused bits have to be cleared (set to logical ?0?). 3c sic1 r/w system interface control 1 300 3d sic2 r/w system interface control 2 301 3e lim3 r/w line interface register 3 302 4 0 sic3 r/w system interface control 3 303 60 dec w disable error counter 304 70 x s1 w transmit signaling register 1 305 71 x s2 w transmit signaling register 2 305 72 x s3 w transmit signaling register 3 305 73 x s 4 w transmit signaling register 4 305 7 4x s5 w transmit signaling register 5 305 75 x s6 w transmit signaling register 6 305 76 x s7 w transmit signaling register 7 305 77 x s 8 w transmit signaling register 8 305 7 8x s 9 w transmit signaling register 9 305 7 9x s10 w transmit signaling register 10 305 7a x s11 w transmit signaling register 11 305 7b x s12 w transmit signaling register 12 305 table 53 t1/j1 control register address arrangement (cont?d) address register type comment page
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 261 2000-07 10.2 detailed description of t1/j1 control registers transmit fifo (write) writing data to x fifocanbedonein 8 -bit (byte) or 16-bit (word) access. the lsb is transmitted first. u p to 32 bytes/16 words of transmit data can be written to the x fifo following an x pr (or alls) interrupt. command register (write) value after reset: 00 h rmc? receive message complete confirmation from cp u to falc ? -lh that the current frame or data block has been fetched following an rpf or rme interrupt, thus the occupied space in the rfifo can be released. rres? receiver reset the receive line interface except the clock and data recovery unit (dpll), the receive framer, the one second timer and the receive signaling controller are reset. however the contents of the control registers is not deleted. receiver reset shall be done after every new device initialization. x rep? transmission repeat if x rep is set together with x tf (write 2 4 h to cmdr), the falc ? -lh repeatedly transmits the contents of the x fifo (1 32 bytes) without hdlc framing fully transparently, i.e. without flag,crc. the cyclic transmission is stopped with an sres command or by resetting x rep. note:during cyclic transmission the xrep-bit has to be set with every write operation to cmdr. 70 x fifo x f7 x f0 (00/01) 70 cmdr rmc rres x rep x res x hf x tf x me sres (02)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 262 2000-07 x res? transmitter reset the transmit framer and transmit line interface excluding the pulse shaper is reset. however the contents of the control registers is not deleted. transmitter reset shall be done after every new device initialization. x hf? transmit hdlc frame afterhavingwrittenupto32bytestothe x fifo, this command initiates the transmission of a hdlc frame. x tf? transmit transparent frame initiates the transmission of a transparent frame without hdlc framing. x me? transmit message end indicates that the data block written last to the transmit fifo completes the current frame. the falc ? -lh can terminate the transmission operation properly by appending the crc and the closing flag sequence to the data. sres? signaling transmitter reset the transmitter of the signaling controller is reset. x fifo is cleared of any data and an abort sequence (seven 1?s) followed by interframe time fill is transmitted. in response to x res an x pr interrupt is generated. signaling transmitter reset shall be done after every new device initialization. this command can also be used by the cp u to abort a frame currently in transmission. note: the maximum time between writing to the cmdr register and the execution of the command takes 2.5 periods of the current system data rate. therefore, if the cpu operates with a very high clock rate in comparison with the falc ? -lh's clock, it is recommended that bit sis.cec should be checked before writing to the cmdr register to avoid any loss of commands. all bits except xrep are cleared automatically.
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 263 2000-07 mode register (read/write) value after reset: 00 h mds2...0? mode select the operating mode of the hdlc controller is selected. 000 reserved 001 reserved 010 1 byte address comparison mode (ral1, 2) 011 2 byte address comparison mode (rah1, 2 and ral1, 2) 100 no address comparison 101 1 byte address comparison mode (rah1, 2) 110 reserved 111 no hdlc framing mode 1 brac? bom receiver active switches the bom receiver to operational or inoperational state. 0 receiver inactive 1 receiver active hrac? hdlc receiver active switches the hdlc receiver to operational or inoperational state. 0 receiver inactive 1 receiver active 70 mode mds2 mds1 mds0 brac hrac (03)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 26 4 2000-07 receive address byte high register 1 (read/write) value after reset: fd h in operating modes that provide high byte address recognition, the high byte of the received address is compared with the individually programmable values in rah1 and rah2. rah1 value of the first individual high address byte bit 1 (c/r-bit) is excluded from address comparison. receive address byte high register 2 (read/write) value after reset: ff h rah2? value of second individual high address byte receive address byte low register 1 (read/write) value after reset: ff h ral1? value of first individual low address byte 710 rah1 0 (0 4 ) 70 rah2 (05) 70 ral1 (06)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 265 2000-07 receive address byte low register 2 (read/write) value after reset: ff h ral2... value of the second individually programmable low address byte. interrupt port configuration (read/write) value after reset: 01 h u nused bits have to be cleared. vis? masked interrupts visible 0 masked interrupt status bits are not visible 1 masked interrupt status bits are visible sci? status change interrupt 0 interrupts isr2.los, isr2.ais and isr0.pden is generated only on the rising edge of the corresponding status flag. 1 interrupts isr2.los, isr2.ais and isr0.pden is generated on the rising and falling edge of the corresponding status flag. ic1...0? interrupt port configuration these bits define the function of the interrupt output stage (pin int): 70 ral2 (07) 70 ipc vis sci ic1 ic0 (0 8 ) ioc1 ioc0 function x 0 1 0 1 1 open drain output 1) push/pull output, active low push/pull output, active high 1) an external pullup resistor is required at pin int
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 266 2000-07 common configuration register 1 (read/write) value after reset: 00 h sflg? enable shared flags if this bit is set, the closing flag of a preceding hdlc frame simultaneously is used as the opening flag of the following frame. 0? shared flag function disabled 1? shared flag function enabled brm? bom receive mode (significant in bom mode only) 0 10 byte packets 1 continuous reception edl x ? enable dl bit access via the transmit fifo a one in this bit position enables the internal dl-bit access via the receive/transmit fifo of the signaling controller. fmr1.edl has to be cleared. eits? enable internal time slot 0-31 signaling 0? internal signaling in time slots 0-31 defined via registers rtr1... 4 or ttr1... 4 is disabled. 1? internal signaling in time slots 0-31 defined via registers rtr1... 4 or ttr1... 4 is enabled. itf? interframe time fill determines the idle ( = no data to send) state of the transmit data coming from the signaling controller. 0 continuous logical ?1? is output 1 continuous flag sequences are output (?01111110? bit patterns) rft1...0? rfifo threshold level the size of the accessible part of rfifo can be determined by programming these bits. the number of valid bytes after an rpf interrupt is given in the following table: 70 ccr1 sflg brm edl x eits itf rft1 rft0 (0 9 )
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 267 2000-07 the value of rft 1,0 can be changed dynamically ? if reception is not running or ? after the current data block has been read, but before the command cmdr.rmc is issued (interrupt controlled data transfer). note:it is seen that changing the value of rft1,0 is possible even during the reception of one frame. the total length of the received frame can be always read directly in rbcl, rbch after an rpf interrupt, except when the threshold is increased during reception of that frame. the real length can then be inferred by noting which bit positions in rbcl are reset by an rmc command (see table below ): rft1 rft0 size of accessible part of rfifo 0 0 1 1 0 1 0 1 32 bytes (reset value) 16 bytes 4 bytes 2bytes rft1 rft0 bit positions in rbcl reset by a cmdr.rmc command 0 0 1 1 0 1 0 1 rbc 4 . 0 rbc3 0 rbc1,0 rbc0
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 26 8 2000-07 common configuration register 3 (read/write) value after reset: 00 h u nused bits have to be cleared. pre1...0? number of preamble repetitions if preamble transmission is enabled, the preamble defined by register pre is transmitted: 00... 1 time 01... 2 times 10... 4 times 11... 8 times ept? enable preamble transmission this bit enables transmission of preamble. the preamble is started after interframe timefill transmission has been stopped and a new frame is to be transmitted. the preamble consists of an 8 -bit pattern repeated a number of times. the pattern is defined by register pre, the number of repetitions is selected by bits pre0 and pre1. note: the ? shared flag ? feature is not influenced by preamble transmission. zero bit insertion is disabled during preamble transmission. radd? receive address pushed to rfifo if this bit is set, the received hdlc address information (1 or 2 bytes, depending on the address mode selected via mode.mds0) is pushed to rfifo. see chapter 8.1 on page 169 for detailed description. rcrc? receive crc on/off if this bit is set, the received crc checksum is written to rfifo (crc-it u -t: 2 bytes). the checksum, consisting of the 2 last bytes in the received frame, is followed in the rfifo by the status information byte (contents of register rsis). the received crc checksum is additionally checked for correctness. if non-auto mode is selected, the limits for ?valid frame? check are modified (refer to rsis.vfr and to chapter 8.1 on page 169 ). 70 ccr3 pre1 pre0 ept radd rcrc x crc (0a)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 26 9 2000-07 x crc? transmit crc on/off if this bit is set, the crc checksum is not generated internally. it has to be written as the last two bytes in the transmit fifo ( x fifo). the transmitted frame is closed automatically with a closing flag. note: the falc ? -lh does not check whether the length of the frame, i.e. the number of bytes to be transmitted makes sense or not. preamble register (read/write) value after reset: 00 h pre0...7? preamble register this register defines the pattern which is sent during preamble transmission (refer to ccr3). lsb is sent first. note: zero bit insertion is disabled during preamble transmission. 70 pre (0b)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 270 2000-07 receive timeslot register 1...4 (read/write) value after reset: 00 h ,00 h ,00 h ,00 h ts0?ts31? timeslot register these bits define the received time slots on the system highway port rdo to be extracted. additionally these registers control the rsigm marker which can be forced high during the respective time slots independently of bit ccr1.eits. a one in the rtr1... 4 bits samples the corresponding time slot in the rfifo of the signaling controller, if bit ccr1.eits is set. assignments: sic1.srsc = 0:(scl k r =8 .1 9 2mhz) ts0 time slot 0 ? ts31 time slot 31 sic1.srsc = 1:(scl k r = 1.5 44 mhz) ts0 time slot 1 ? ts23 time slot 2 4 0 normal operation. 1? the contents of the selected time slot is stored in the rfifo. although the idle time slots can be selected. this function is activated, if bit ccr1.eits is set. the corresponding time slot is forced high on pin rsigm. 70 rtr1 ts0 ts1 ts2 ts3 ts 4 ts5 ts6 ts7 (0c) rtr2 ts 8 ts 9 ts10 ts11 ts12 ts13 ts1 4 ts15 (0d) rtr3 ts16 ts17 ts1 8 ts1 9 ts20 ts21 ts22 ts23 (0e) rtr 4 ts2 4 ts25 ts26 ts27 ts2 8 ts2 9 ts30 ts31 (0f)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 271 2000-07 transmit timeslot register 1...4 (read/write) value after reset: 00 h ,00 h ,00 h ,00 h ts0?ts31? transmit timeslot register these bits define the transmit time slots on the system highway to be inserted. additionally these registers control the x sigm marker which can be forced high during the respective time slots independently of bit ccr1.eits. a one in the ttr1... 4 bits inserts the corresponding time slot sourced by the x fifo in the data received on pin x di, if bit ccr1.eits is set. if sic3.ttrf is set and ccr1.edl x /eits = 00, insertion of data received on port x sigiscontrolledbythisregisters. assignments: sic1.srsc = 0:(scl k r =8 .1 9 2mhz) ts0 time slot 0 ? ts31 time slot 31 sic1.srsc = 1:(scl k r = 1.5 44 mhz) ts0 time slot 1 ? ts23 time slot 2 4 0 normal operation 1? the contents of the selected time slot is inserted into the outgoing data stream from x fifo. this function is activated only, if bit ccr1.eits is set. the corresponding time slot is forced high on marker pin x sigm. 70 ttr1 ts0 ts1 ts2 ts3 ts 4 ts5 ts6 ts7 (10) ttr2 ts 8 ts 9 ts10 ts11 ts12 ts13 ts1 4 ts15 (11) ttr3 ts16 ts17 ts1 8 ts1 9 ts20 ts21 ts22 ts23 (12) ttr 4 ts2 4 ts25 ts26 ts27 ts2 8 ts2 9 ts30 ts31 (13)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 272 2000-07 interrupt mask register 0...5 value after reset: ff h ,ff h ,ff h ,ff h ,ff h imr0...5... interrupt mask register each interrupt source can generate an interrupt signal on port int (characteristics of the output stage are defined via register ipc). a ?1? in a bit position of imr0?5 sets the mask active for the interrupt status in isr0?3 and isr5. masked interrupt statuses neither generate a signal on int, nor are they visible in register gis. moreover, they are ? not displayed in the interrupt status register if bit ipc.vis is cleared ? displayed in the interrupt status register if bit ipc.vis is set. after reset, all interrupts are dis abled. framer mode register 0 (read/write) value after reset: 00 h x c1?0? transmit code serial code transmitter is independent to the receiver. 00? nr z (optical interface) 01? not assigned 70 imr0 rme rfs isf rmb rsc crc6 pden rpf (1 4 ) imr1 case rdo alls x d ux mb x lsc x pr (15) imr2 far lfa mfar lmfa ais los rar ra (16) imr3 es sec x slp llbsc rsn rsp (17) imr 4 lfa fer cer ais los cve slip (1 8 ) imr5 x sp x sn (1 9 ) 70 fmr0 x c1 x c0 rc1 rc0 frs sraf e x ls sim (1a)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 273 2000-07 10?ami coding with z ero code suppression ( z cs, b7-stuffing). disabling of the z cs is done by activating the clear channel mode via register ccb1...3. (ternary or digital interface) 11?b 8z s code (ternary or digital dual rail interface) rc1?0? receive code serial code receiver is independent to the transmitter. 00? nr z (optical interface) 01? not assigned 10? ami coding (ternary or digital dual rail interface) 11? b 8z s code (ternary or digital dual rail interface) frs? force resynchronization a transition from low to high forces the frame aligner to execute a resynchronization of the pulse frame. in the asynchronous state, a new frame position is assumed at the next candidate if there is one. otherwise, a new frame search with the meaning of a general reset is started. in the synchronous state this bit has the same meaning as bit fmr0.e x ls except if fmr2.mcsp = 1. this bit is not reset automatically. sraf? select remote (yellow) alarm format for f12 and esf format 0? f12: bit2 = 0 in every channel. esf: pattern ?1111 1111 0000 0000?? in data link channel. 1? f12: fs bit of frame 12. esf: bit2 = 0 in every channel e x ls? external loss of frame with a low to high transition a new frame search is started. this has the meaning of a general reset of the internal frame alignment unit. synchronous state is reached only if there is one definite framing candidate. in the case of multiple candidates, the setting of the bit fmr0.frs forces the receiver to lock onto the next available framing position. this bit is not reset automatically. sim? alarm simulation setting/resetting this bit initiates internal error simulation of: ais (blue alarm), loss of signal (red alarm), loss of frame alignment, remote (yellow) alarm, slip, framing errors, crc errors, code violations. the error counters fec, cvc, cec, ebc are incremented. the selection of simulated alarms is done via the error simulation counter: frs2.esc2...0 which are incremented with each setting of bit fmr0.sim. for complete checking of the alarm indications eight
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 27 4 2000-07 simulation steps are necessary (frs2.esc2...0 = 0 after a complete simulation). framer mode register 1 (read/write) value after reset: 00 h ctm? channel translation mode 0? channel translation mode 0 1? channel translation mode 1 see table 26 on page 113 for details. sigm? select signaling mode 0? normal operation (no bit-robbing). 1? cas bit-robbing mode selected note: bit fmr5.eibr has also to be set, if bit-robbing mode is to be used. edl? enable dl-bit access via register x dl1...3 only applicable in f 4 ,f2 4 or f72 frame format. 0? normal operation. the dl-bits are taken from system highway or if enabled via ccr1.edl x from the x fifo of the signaling controller. 1? dl-bit register access. the dl-bit information is taken from the registers x dl1...3 and overwrites the dl-bits received at the system highway (pin x di) or the internal x fifo of the signaling controller. however, transmitting contents of registers x dl1...3 is disabled if transparent mode is enabled (fmr 4 .tm). pmod? pcm mode for t1/j1 applications this bit must be set high. switching into t1/j1 mode the device needs up to 10 s to settle up to the internal clocking. 0? pcm 30 or e1 mode. 1? pcm 2 4 or t1/j1 mode. 70 fmr1 ctm sigm edl pmod crc ecm imod x ais (1b)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 275 2000-07 crc? enable crc6 this bit is only significant when using the esf format. 0 crc6 check/generation disabled. for transmit direction, all crc bit positions are set. 1 crc6 check/generation enabled. ecm? error counter mode the function of the error counters (fec,cec,cvc,ebc) is determined by this bit. 0 before reading an error counter the corresponding bit in the disable error counter register (dec) has to be set. in 8 bit access the low byte of the error counter should always be read before the high byte. the error counters are reset with the rising edge of the corresponding bits in the dec register. 1? every second the error counter is latched and then automatically be reset. the latched error counter state should be read within the next second. reading the error counter during updating should be avoided (do not access an error counter within 2 s before or after the one-second interrupt occurs). imod? system interface mode 0? 4 .0 9 6mbit/s 1?2.0 48 mbit/s or 1.5 44 mbit/s this bit has to be set if sic1.srsc or sic1.s x sc are set. x ais? transmit ais towards remote end sends ais (blue alarm) via ports: x l1, x l2 towards the remote end. if local loop mode is enabled the transmitted data is looped back to the system internal highway without any changes.
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 276 2000-07 framer mode register 2 (read/write) value after reset: 00 h mcsp? multiple candidates synchronization procedure ssp? select synchronization/resynchronization procedure together with bit fmr2.ssp the synchronization mode of the receive framer is defined: mcsp/ssp: 00? f12/72 format: specified number of errors in both ft framing and fs framing lead to loss of sync (frs0.lfa is set). in the case of fs bit framing errors, bit frs0.lmfa is set additionally. a complete new synchronization procedure is initiated to regain pulseframe alignment and then multiframe alignment. f2 4 : normal operation: synchronization is achieved only on verification the framing pattern. 01? f12/72: specified number of errors in ft framing has the same effect as above. specified number of errors in fs framing only initiates a new search for multiframe alignment without influencing pulseframe synchronous state (frs0.lmfa is set). f2 4 : synchronous state is reached when three consecutive multiframe pattern are correctly found independent of the occurrence of crc6 errors. 10? f2 4 : a one enables a synchronization mode which is able to choose multiple framing pattern candidates step by step. i.e. if in synchronous state the crc error counter indicates that the synchronization might have been based on an alias framing pattern, setting of fmr0.frs leads to synchronization on the next candidate available. however, only the previously assumed candidate is discarded in the internal framing pattern memory. the latter procedure can be repeated until the 70 fmr2 mcsp ssp dais sais plb a x ra e xz e (1c)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 277 2000-07 framer has locked on the right pattern (no extensive crc errors). therefor bit fmr1.crc must be set. 11? f2 4 : synchronization is achieved on verification of the framing pattern and the crc6 bits. synchronous state is reached when framing pattern and crc6 checksum are correctly found. for correct operation the crc check must be enabled by setting bit fmr1.crc6. dais? disable ais to system interface 0? ais is automatically inserted into the data stream to rdo if falc ? -lh is in asynchronous state. 1? automatic ais insertion is disabled. furthermore, ais insertion can be initiated by programming bit fmr2.sais. sais? send ais towards system interface sends ais (blue alarm) via output rdo towards system interface. this function is not influenced by bit fmr2.dais. plb? payload loop back 0 normal operation. payload loop is disabled. 1? the payload loopback loops the data stream from the receiver section back to transmitter section. looped data is output on pin rdo. data received on port x di, x sig, s y p x and x mfs are ignored. with fmr 4 .tm = 1all1 9 3 bits per frame are looped back. if fmr 4 .tm = 0 the dl- or fs- or crc-bits are generated internally. ais is sent immediately on port rdo by setting the fmr2.sais bit. during payload loop is active the receive time slot offset (registers rc1...0) should not be changed. it is recommended to write the actual value of x c1 into this register once again, because a write access to register x c1 sets the read/write pointer of the transmit elastic buffer into its optimal position to ensure a maximum wander compensation (the write operation forces a slip). a x ra? automatic transmit remote alarm 0 normal operation 1? the remote alarm (yellow alarm) bit is set automatically in the outgoing data stream if the receiver is in asynchronous state (frs0.lfa bit is set). in synchronous state the remote alarm bit is reset.
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 27 8 2000-07 e xz e? excessive z eros detection enable selects error detection mode in the bipolar receive bit stream. 0? only bipolar violations are detected. 1? bipolar violations and zero strings of 8 or more contiguous zeros in b 8z s code or more than 15 contiguous zeros in ami code are detected additionally and counted in the code violation counter cvc. channel loop back register (read/write) value after reset: 00 h spn? select additional optical pin functions together with bit lim3.es y the functionality of pin 8 0 is defined: programming of loop.spn and lim3.es y and the corresponding pin function is shown below. spn/es y : 00? function of pin 8 0 x sig: if sic3.ttrf = 1, transmit data from the system interface. internal multiplexing with the x di data stream is controlled by x sigm. no input function defined for sic3.ttrf = 0. 01? function of pin 8 0s y nc2: external synchronization input for the dco- x circuitry 10? function of pin 8 0roid:receiveopticalinterfacedata (input) and pin 6 8 : x mfb/ x oid transmit optical interface data (output). at the same time data received on pin 2 are ignored, data on pin x oid (pin 15) are undefined. transmit data is clocked off with the positive transition of x cl k . after reset the transmit multiframe begin marker is output on pin 6 8 . 11? function of pin 8 0 x sig: the signaling information from thetransmitsysteminterfaceisreceivedonpin x sig. bit fmr5.eibr should be cleared to disable internal signaling access from registers x s1...12. the signaling information from the line interface is transmitted on pin rsig. 70 loop spn rtm eclb cla 4 cla3 cla2 cla1 cla0 (1d)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 27 9 2000-07 rtm? receive transparent mode setting this bit disconnects control of the internal elastic store from the receiver. the elastic store is now in a ?free running? mode without any possibility to update the time slot assignment to a new frame position in case of re-synchronization of the receiver. this function can be used in conjunction with the ?disable ais to system interface? feature (fmr2.dais) to realize undisturbed transparent reception. this bit should be enabled in case of unframed data reception mode. after resetting rtm to 0, the elastic buffer is adjusted after the next resynchronization. eclb? enable channel loop back 0? disables the channel loop back. 1? enables the channel loop back selected by this register. cla4?0? channel address for loop back cla = 1?2 4 selects the channel. during loop back, the contents of the associated outgoing channel on ports x l1/ x dop/ x oid and x l2/ x don is equal to the idle channel code programmed in register idle. framer mode register 4 (read/write) value after reset: 00 h ais3? select ais condition 0? ais (blue alarm) is indicated (frs0.ais) when two or less zeros in the received bit stream are detected in a time interval of 12 frames (f 4 , f12, f72) or 2 4 frames (esf). 1? ais (blue alarm) detection is only enabled when falc ? -lh is in asynchronous state. the alarm is indicated (frs0.ais) when ? three or less zeros within a time interval of 12 frames (f 4 , f12, f72), or ? five or less zeros within a time interval of 2 4 frames (esf) are detected in the received bit stream. 70 fmr 4 ais3 tm x ra ssc1 ssc0 a u to fm1 fm0 (1e)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 2 8 0 2000-07 tm? transparent mode setting this bit enables the transparent mode: in transmit direction bit 8 of every fs/dl time slot from the system internal highway ( x di) is inserted in the f-bit position of the outgoing frame. internal framing generation, insertion of crc and dl data is disabled. in receive direction the framing bit is also forwarded to rdo and inserted into the fs/dl time slot. bit rdcf (bit 1 of fs/dl time slot) indicates a dl bit. x ra? transmit remote alarm (yellow alarm) if high, remote alarm is sent via pcm route. clearing the bit removes the remote alarm pattern. remote alarm indication depends on the multiframe structure as follows: f 4 :bit2 = 0 in every speech channel f12: fmr0.sraf = 0: bit2 = 0 in every speech channel fmr0.sraf = 1:fs-bitofframe12isforcedto?1? esf: fmr0.sraf = 0: pattern ?1111111100000000 11111111000?? in data link channel fmr0.sraf = 1: bit2 = 0 in every speech channel f72: bit2 = 0 in every speech channel ssc1...0? select sync conditions loss of frame alignment (frs0.lfa or opt. frs0.lmfa) is declared if 00 = 2 out of 4 framing bits 01 = 2 out of 5 framing bits 10 = 2 out of 6 framing bits in f 4 /12/72 format 10 = 2 out of 6 framing bits per multiframe period in esf format 11 =4 consecutive multiframe pattern in esf format are incorrect. it depends on the selected multiframe format and optionally on bit fmr2.ssp which framing bits are observed: f 4 :ftbits frs0.lfa f12, f72: ssp = 0: ft bits frs0.lfa: fs bits frs0.lfa and frs0.lmfa ssp = 1:ft frs0.lfa fs frs0.lmfa esf: esf framing bits frs0.lfa
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 2 8 1 2000-07 auto? enable auto resynchronization 0? the receiver does not resynchronize automatically. starting a new synchronization procedure is possible via the bits: fmr0.e x ls or fmr0.frs. 1? auto-resynchronization is enabled. fm1?0? select frame mode fm = 0: 12-frame multiframe format (f12, d3/ 4 ) fm = 1: 4 -frame multiframe format (f 4 ) fm = 2: 2 4 -frame multiframe format (esf) fm = 3: 72-frame multiframe format (f72, remote switch mode) framer mode register 5 (read/write) value after reset: 00 h srs? signaling register size valid in f12/f72 frame format only 0? signaling access is done via registers rs/ x s1...6 1? signaling access is done via increased register bank rs/ x s1...12 eibr? enable internal bit-robbing access 0? normal operation (no bit-robbing). 1? cas bit-robbing mode selected note: bit fmr1.sigm has also to be set, if bit-robbing mode is to be used. x ld? transmit line loopback (llb) down code 0? normal operation. 1? a one in this bit position causes the transmitter to replace normal transmit data with the llb down (deactivate) code continuously until this bit is reset. the llb down code is optionally overwritten by the framing/dl/crc bits. for correct operation bit fmr5. x l u must be cleared 70 fmr5 srs eibr x ld x l u sro x tm rtf (1f)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 2 8 2 2000-07 x lu? transmit llb up code 0? normal operation. 1? a one in this bit position causes the transmitter to replace normal transmit data with the llb u p (activate) code continuously until this bit is reset. the llb u p code is optionally overwritten by the framing/dl/crc bits. for correct operation bit fmr5. x ld must be cleared. sro? signaling register organization valid in f12/f72 and esf frame format only 0? signaling access via registers rs/ x s1...12 is done without reordering of abcd bits. 1? signaling access via registers rs/ x s1...12 is done with reordering of abcd bits. for details see description of registers x s1...12 on page 305 and rs1...12 on page 333 x tm? transmit transparent mode valid if loop-timed mode is enabled (lim2.elt = 1). 0?ports s y p x / x mfs define the frame/multiframe begin on the transmit system highway. the transmitter is usually synchronized on this externally sourced frame boundary and generates the fas bits according to this framing. any change of the transmit time slot assignment or a transmit slip subsequently produces a change of the fas bit positions. 1? disconnects the control of the transmit system interface from the transmitter. the transmitter is now in a free running mode without any possibility to update the multiframe position. the framing (fas bits) generated by the transmitter is not disturbed (in case of changing the transmit time slot assignment or transmit slip) by the transmit system highway unless register x c1 is written. u seful in loop-timed applications. for correct operation the transmit elastic buffer (2 frames, sic1. x bs1/0 = 10) has to be enabled rtf? receive transparent forwarding setting this bit all 1 9 3 bits per frame of the incoming multiframe are forwarded to pin rdo transparently. in asynchronous state the received data may be transparently switched through if bit fmr2.dais is set.
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 2 8 3 2000-07 transmit control 0 (read/write) value after reset: 00 h brm? enable bit-robbing marker a one in this bit marks the robbed bit positions on the system highway. rsigm marks the receive and x sigm marks the transmit robbed bits. for correct operation bit fmr1.sigm must be set. mfbs? enable pure multiframe begin signals valid only if esf or f72 format is selected. if set, signals rmfb and x mfb indicate only the multiframe begin. additional pulses (every 12 frames) are disabled. sfr z ? select freeze output 0? signal rfsp is output on port rfsp /free z s 1? freeze status signal is output on port rfsp /free z s x co2? x co0? transmit clock slot offset initial value loaded into the transmit bit counter at the trigger edge of scl kx when the synchronous pulse on port s y p x is active. setting of sic1.s x sc enforces programming the offset values in the range of0to1 9 2 bits with x co0 always cleared. 70 x c0 brm mfbs sfr zx co2 x co1 x co0 (20)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 2 84 2000-07 transmit control 1 (read/write) value after reset: 00 h a write access to this address resets the transmit elastic buffer to its basic starting position. therefore, updating of the value should only be done when the falc ? -lh is initialized or when the buffer should be centered. as a consequence a transmit slip occurs. x cos? transmit clock offset shift valid only if sic1.s x sc = 0 0? the delay t between the beginning of time slot 0 and the initial edge of scl kx (after s y p x goes active) is an even number in the range of 0 to 1022 scl kx cycles. 1? the delay t is an odd number in the range of 1 to 1023 scl kx cycles. x to5? x to0? transmit time slot offset initial value loaded into the transmit bit counter at the trigger edge of scl kx when the synchronous pulse on port s y p x is active. setting of sic1.s x sc enforces programming the offset values in the range of0to1 9 2bits. receive control 0 (read/write) value after reset: 00 h rcos? receive clock offset valid only if sic1.s x sc = 0 0 the delay t between the beginning of time slot 0 and the initial edge of scl k r(afters y p x goes active) is an even number in the range of 0 to 1022 scl kx cycles. 1? the delay t is an odd number in the range of 1 to 1023 scl kx cycles. 70 x c1 x cos x to5 x to 4x to3 x to2 x to1 x to0 (21) 70 rc0 rcos sics crci x crci rdis rco2 rco1 rco0 (22)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 2 8 5 2000-07 sics? system interface channel select applicable only if bit fmr1.imod ( 4 -mhz system interface) is cleared. 0 received data is output on port rdo in the first channel phase. data in the second channel phase is tristated. data on pin x di is sampled in the first channel phase only. data in the second channel phase is ignored. 1 received data is output on port rdo in the second channel phase. data in the first channel phase is tristated. data on pin x di is sampled in the second channel phase only. data in the first channel phase is ignored. crci? automatic crc6 bit inversion if set, all crc bits of one outgoing extended multiframe are inverted in case a crc error is flagged for the previous received multiframe. this function is logically ored with rc0. x crci. x crci? transmit crc6 bit inversion if set, the crc bits in the outgoing data stream are inverted before transmission. this function is logically ored with rc0.crci. rdis? receive data input sense only applicable for dual rail mode (lim1.drs = 1). 0 inputs: rdip, rdin active low, input roid is active high 1 inputs: rdip, rdin active high, input roid is active low rco2?rco0? receive offset/receive frame marker offset depending on bit sic2.srfso this bit enables different functions: receive clock-slot offset (sic2.srfso = 0) initial value loaded into the receive bit counter at the trigger edge of scl k r when the synchronous pulse on port s y pr is active. setting of sic1.srsc enforces programming the offset values in a range of 0to1 9 2 bits with rco0 always cleared. receive frame marker offset (sic2.srfso = 1) offset programming of the receive frame marker which is output on port s y pr . the receive frame marker could be activated during any bit position of the current frame. calculation of the value x of the ?receive counter offset? register rc1/0 depends on the bit position bp which should be marked and scl k r: x= (2bp) mod 386 ,forscl k r = 1.5 44 mhz
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 2 8 6 2000-07 receive control 1 (read/write) value after reset: 00 h sjr? select japanese itu-t requirements for esf format 0 alarm handling and crc6 generation/checking is done according it u -t g. 70 4+ 706 1 alarm handling and crc6 generation/checking is done according it u -t jg. 70 4+ 706 see table 48 " framer initialization (t1/j1) " on page 166 for more details. rram? receive remote alarm mode the conditions for remote (yellow) alarm (frs0.rra) detection can be selected via this bit to allow detection even in the presence of ber 10 ** -3: rram = 0 detection f 4 :bit2 = 0 in every speech channel per frame. f12: fmr0.sraf = 0: bit2 = 0 in every speech channel per frame. fmr0.sraf = 1: s-bit of frame 12 is forced to ?1? esf: fmr0.sraf = 0: pattern ?1111 1111 0000 0000?? in data link channel fmr0.sraf = 1: bit2 = 0 in every speech channel f72: bit2 = 0 in every speech channel per frame. release the alarm is reset when above conditions are no longer detected. rram = 1 detection f 4 :bit2 = 0 in 255 consecutive speech channels. f12: fmr0.sraf = 0: bit 2 = 0 in 255 consecutive speech channels. fmr0.sraf = 1: s-bit of frame 12 is forced to ?1? esf: fmr0.sraf = 0: pattern ?1111 1111 0000 0000?? in data link channel fmr0.sraf = 1: bit 2 = 0 in 255 consecutive speech channels f72: bit 2 = 0 in 255 consecutive speech channels. 70 rc1 sjr rram rto5 rto 4 rto3 rto2 rto1 rto0 (23)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 2 8 7 2000-07 release: depending on the selected multiframe format the alarm is reset when falc-lh does not detect ? the ?bit 2 = 0? condition for three consecutive pulse frames (all formats if selected), ? the ?fs bit? condition for three consecutive multiframes (f12), ? the ?dl pattern? for three times in a row (esf). rto5?rto0? receive time-slot offset/receive frame marker offset depending on bit sic2.srfso this bit enables different functions: receive time-slot offset (sic2.srfso = 0) initial value which is loaded into the receive time-slot counter at the trigger edge of scl k r when the synchronous pulse on port s y pr is active. setting of sic1.srsc enforces programming the offset values inarangeof0to1 9 2bits. receive frame marker offset (sic2.srfso = 1) offset programming of the receive frame marker which is output on port s y pr . the receive frame marker could be activated during any bit position of the current frame. calculation of the value x of the ?receive counter offset? register rc1/0 depends on the bit position bp which should be marked and scl k r: x= (2bp) mod 386 ,forscl k r = 1.5 44 mhz
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 2 88 2000-07 transmit pulse-mask 2?0 (read/write) value after reset: 9 c h ,03 h ,00 h the transmit pulse shape which is defined in ansi t1. 102 is output on pins x l1 and x l2. the level of the pulse shape can be programmed via registers x pm2...0 to create a custom waveform. in order to get an optimized pulse shape for the external transformers each pulse shape is divided internally into four sub pulse shapes. in each sub pulse shape a programmed 5 bit value defines the level of the analog voltage on pins x l1/2. together four 5 bit values have to be programmed to form one complete transmit pulse shape.the four 5 bit values are sent in the following sequence: x p0 4 -00: first pulse shape level x p1 4 -10: second pulse shape level x p2 4 -20: third pulse shape level x p3 4 -30: fourth pulse shape level changing the lsb of each subpulse in registers x pm2...0 changes the amplitude of the differential voltage on x l1/2 by approximately 110 mv. the x pm-values in the following table are based on simulations. they are valid for the following external circuitry: transformer ratio: 1: ; cable: p u lb 22awg (100 ? ) ; serial resistors: 5 ? . adjustment of these coefficients may be necessary for other external conditions. 70 x pm0 x p12 x p11 x p10 x p0 4x p03 x p02 x p01 x p00 (2 4 ) x pm1 x p30 x p2 4x p23 x p22 x p21 x p20 x p1 4x p13 (25) x pm2 x lhp x lt da x lt x p3 4x p33 x p32 x p31 (26) table 54 pulse shaper programming (t1/j1) range in m range in ft. x pm0 x pm1 x pm2 x p04- x p00 x p14- x p10 x p24- x p20 x p34- x p30 hexadecimal decimal 0... 4 0 0...133 1 99 b01252 4 63 4 0... 8 1 133...266 5b 9 f0127267 3 8 1...122 266...3 99 7d ab 01 2 9 27 10 3 122...162 3 99 ...533 7f b7 01 31 27 13 3 162...200 533...655 5f bb 01 31 26 1 4 3 2
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 2 89 2000-07 x lhp? transmit line high power with this bit the output current capability of transmit lines x l1/ x l2 is increased. according to the dc characteristics, this bit has to be set, if an output current of more than 60 ma is required. 0? output current low 1? output current high for absolute values see dc characteristics. x lt... transmit line tristate 0 normal operation 1 transmit line x l1/ x l2 or x dop/ x don are switched into high impedance state. if this bit is set the transmit line monitor status information is frozen. da x lt... disable automatic tristating of x l1/2 0... normal operation. if a short is detected on pins x l1/2 the transmit line monitor sets the x l1/2 outputs into a high impedance state. 1... if a short is detected on pins x l1/2 an automatic setting these pins into a high impedance state (by the x l-monitor) is disabled. idle channel code register (read/write) value after reset: 00 h idl7?idl0? idle channel code if channel loop back is enabled by programming the register loop.eclb = 1, the contents of the assigned outgoing channel on ports x l1/ x l2 respective x dop/ x don is set equal to the idle channel code selected by this register. additionally, the specified pattern overwrites the contents of all channels of the outgoing pcm frame selected via the idle channel registers icb1?icb3. idl7 is transmitted first. 70 idle idl7 idl0 (2 9 )
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 2 9 0 2000-07 transmit dl-bit register 1...3 (read/write) value after reset: 00 h ,00 h ,00 h x dl1? x dl3? transmit fs/dl-bit data the dl-bit register access is enabled by setting bits fmr1.edl = 1. with the transmit multiframe begin an interrupt isr1. x mb is generated and the contents of these registers x dl1...3 is copied into a shadow register. the contents is sent out subsequently in the data stream of the next outgoing multiframe if no transparent mode is enabled. x dl10 is sent out first. in f 4 frame format only x dl10...11 are transmitted. in f2 4 frame format x dl10...23 are shifted out. in f72 frame format x dl10...37 are transmitted. the transmit multiframe begin interrupt ( x mb) requests that these registers should be serviced. if requests for new information are ignored, current contents is repeated. clear channel register (read/write) value after reset: 00 h ,00 h ,00 h ch1?ch24? channel selection bits 0? normal operation. bit-robbing information and z ero code suppression ( z cs, b7 stuffing) may change contents of the selected speech/data channel if assigned modes are enabled via bits fmr5.eibr and fmr0. x c1/0. 1? clear channel mode. contents of selected speech/data channel is not overwritten by internal or external bit-robbing and 70 x dl1 x dl17 x dl16 x dl15 x dl1 4x dl13 x dl12 x dl11 x dl10 (2a) x dl2 x dl27 x dl26 x dl25 x dl2 4x dl23 x dl22 x dl21 x dl20 (2b) x dl3 x dl37 x dl36 x dl35 x dl3 4x dl33 x dl32 x dl31 x dl30 (2c) 70 ccb1 ch1 ch2 ch3 ch 4 ch5 ch6 ch7 ch 8 (2d) ccb2 ch 9 ch10 ch11 ch12 ch13 ch1 4 ch15 ch16 (2e) ccb3 ch17 ch1 8 ch1 9 ch20 ch21 ch22 ch23 ch2 4 (2f)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 2 9 1 2000-07 z cs information. transmission of channel assigned signaling and control of pulse density is applied by the user. idle channel register (read/write) value after reset: 00 h ,00 h ,00 h ,00 h ic1?ic24? idle channel selection bits these bits define the channels (time slots) of the outgoing pcm frame to be altered. 0? normal operation. 1? idle channel mode. the contents of the selected channel is overwritten by the idle channel code defined via register idle. line interface mode 0 (read/write) value after reset: 00 h x fb? transmit full bauded mode only applicable for dual rail mode (bit lim1.drs = 1). 0?output signals x dop/ x don are half bauded (normal operation). 1?output signals x dop/ x don are full bauded. x dos? transmit data out sense only applicable for dual rail mode (bit lim1.drs = 1) 0? output signals x dop/ x don are active low. output x oid is active high (normal operation). 1? output signals x dop/ x don are active high. output x oid is active low. 70 icb1 ic1 ic2 ic3 ic 4 ic5 ic6 ic7 ic 8 (30) icb2 ic 9 ic10 ic11 ic12 ic13 ic1 4 ic15 ic16 (31) icb3 ic17 ic1 8 ic1 9 ic20 ic21 ic22 ic23 ic2 4 (32) 70 lim0 x fb x dos scl1 scl0 e q on elos ll mas (3 4 )
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 2 9 2 2000-07 scl1...0? select clock output 00? output frequency on pin cl kx is 20 48 khz active high. 01? output frequency on pin cl kx is 20 48 khz active low. 10? output frequency on pin cl kx is 4 0 9 6 khz active high. 11? output frequency on pin cl kx is 4 0 9 6 khz active low. eqon? receive equalizer on 0? -10 db receiver: short haul mode 1? -36 db receiver: long haul mode elos? enable loss of signal 0? normal operation, the extracted receive clock is output on pin rcl k 1? during of loss of signal (frs0.los = 1) output rcl k is set high. ll? local loop 0 normal operation 1 local loop active. the local loopback mode disconnects the receive lines rl1/rl2 (rdip/rdin, respectively) from the receiver. data provided by system interface is routed back to the system interface. the transmitted data is not affected. receiver and transmitter coding must be identical. operates in analog and digital line interface mode. in analog line interface mode data is looped through the complete analog receiver. mas? master mode 0 slave mode 1 master mode on. if this bit is set and the s y nc pin is connected to v ss the falc-lh works as a master for the system. the internal dco?s of the jitter attenuator are centered and the system clocks which are output via cl k8 m/cl kx are stable (divided from the dco frequencies). if a clock (1.5 44 mhz or 2.0 48 mhz) is detected at the s y nc pin the falc-lh synchronizes automatically to this clock. the production tolerance is approximately 30 ppm of the crystal frequency if c load = 15 pf.
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 2 9 3 2000-07 line interface mode 1 (read/write) value after reset: 00 h efsc? enable frame synchronization pulse 0? the transmit clock is output on pin x cl k 1? pin x cl k provides an 8 khz frame synchronization pulse which is active for one 2.0 48 -mhz cycle ( 488 ns) ril2?ril0? receive input threshold only valid if analog line interface and short haul mode is selected (lim1.drs = 0 and lim1.e q on = 0). no signal is declared if the voltage between pins rl1 and rl2 drops below the limits programmed via bits ril2...0 and the received data stream has no transition for a period defined in the pcd register. the threshold where no signal is declared is programmable via the ril2...0 bits. see table 58 " dc parameters " on page 336 for details. note: lim1.ril(2:0) must be programmed before lim0.eqon = 1 is set. dcoc dco-r and dco- x control 0? 1.5 44 -mhz reference clock for the dco-r/dco- x circuitry provided on pin s y nc/s y nc2. 1? 2.0 48 -mhz reference clock for the dco-r/dco- x circuitry provided on pin s y nc/s y nc2. 70 lim1 efsc ril2 ril1 ril0 dcoc jatt rl drs (35)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 2 94 2000-07 jatt?rl... transmit jitter attenuator/remote loop 00 = normal operation. the transmit jitter attenuator is disabled. transmit data bypasses the buffer. 01 = remote loop active without transmit jitter attenuator enabled. transmit data bypasses the buffer. 10 = not assigned 11 = remote loop and jitter attenuator active. received data from pins rl1/2 or rdip/n or roid is sent ?jitter free? on ports x l1/ 2or x dop/n or x oid. the dejittered clock is generated by the dco- x circuitry. drs? dualrailselect 0 = the ternary interface is selected. multifunction ports rl1/2 and x l1/2 become analog in/outputs. 1 = the digital dual rail interface is selected. received data is latched on multifunction ports rdip/rdin while transmit data is output on pins x dop/ x don. pulse count detection register (read/write) value after reset: 00 h pcd7?pcd0? pulse count detection a los alarm (red alarm) is detected if the incoming data stream has no transitions for a programmable number t consecutive pulse positions. the number t is programmable via the pcd register and canbecalculatedasfollows: t = 16(n + 1) ; with 0 n 255. the maximum time is: 256 16 6 48 ns = 2.65 ms. every detected pulse resets the internal pulse counter. the counter is clocked with the receive clock rcl k . 70 pcd pcd7 pcd0 (36)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 2 9 5 2000-07 pulse count recovery (read/write) value after reset: 00 h pcr7?pcr0? pulse count recovery a los alarm (red alarm) is cleared if a pulse density is detected in the received bit stream.the number of pulses m which must occur in the predefined pcd time interval is programmable via the pcr register and can be calculated as follows: m = n + 1 ; with 0 n 255. the time interval starts with the first detected pulse transition. with every received pulse a counter is incremented and the actual counter is compared with the contents of pcr register. if the pulse number is the pcr value the los alarm is reset otherwise the alarm stays active. in this case the next detected pulse transition starts a new time interval. an additional loss of signal recovery condition may be selected by register lim2.los2...1. line interface mode 2 (read/write) value after reset: 00 h lbo2...lbo1? line build-out in long haul applications lim0.e q on = 1 a transmit filter can be optionally placed on the transmit path to attenuate the data on pins x l1/2. selecting the transmitter attenuation is possible in steps of 7.5 db@772khzwhichisaccordingtofcc6 8 or ansi t1. 4 03. to meet the line build-out defined by ansi t1. 4 03 registers x pm2...0 should be programmed as follows: 00? 0 db 01? -7.5 db -- >x pm2...0 = 20 h ,02 h ,11 h 10? -15 db -- >x pm2...0 = 20 h ,01 h , 8 e h 11? -22.5 db -- >x pm2...0 = 20 h ,01 h ,0 9 h 70 pcr pcr7 pcr0 (37) 70 lim2 lbo2 lbo1 dja2 dja1 scf elt los2 los1 (3 8 )
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 2 9 6 2000-07 dja2? digital jitter attenuation dco- x 0? jitter attenuation of the transmit clock is done using an external pullable crystal between pins x tal3/ 4 1? jitter attenuation of the transmit clock is done without using an external pullable crystal between pins x tal3/ 4 . only a free running 12.352-mhz clock has top be provided at x tal3 ( + /- 50 ppm). dja1? digital jitter attenuation dco-r 0? jitter attenuation of the system/transmit clock is done using an external pullable crystal between pins x tal1/2 1? jitter attenuation of the system/transmit clock is done without using an external pullable crystal between pins x tal1/2. only a free running 16.3 84 -mhzclockhastopbeprovidedat x tal1. scf? select corner frequency of dco-r setting this bit reduces the corner frequency of the dco-r circuit by the factor of ten to 0.6 hz. reducing the corner frequency of the dco-r circuitry increases the synchronization time before the frequencies are synchronized. elt? enable loop-timed 0? normal operation 1? transmit clock is generated from the clock supplied by x tal3 which is synchronized with the extracted receive route clock. in this configuration the transmit elastic buffer has to be enabled. refer to register fmr5. x tm. for correct operation of loop timed the remote loop (bit lim1.rl = 0) must be inactive. los2...1? loss of signal recovery condition 00? the los alarm is cleared if the predefined pulse density (register pcr) is detected during the time interval which is defined by register pcd. 01? additionally to the recovery condition described above a los alarm is only cleared if the pulse density is fulfilled and no more than 15 contiguous zeros are detected during the recovery interval. (according to tr-nwt 499 ). 10? clearing of a los alarm is done if the pulse density is fulfilled andnomorethan 99 contiguous zeroes are detected during the recovery interval (according to tr-nwt 8 20). 11? not assigned
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 2 9 7 2000-07 loop code register 1 (read/write) value after reset: 00 h eprm? enable pseudo random bit sequence monitor 0? pseudo random bit sequence (prbs) monitor is disabled. 1? prbs monitor is enabled. setting this bit enables incrementing the cec2 error counter with each detected prbs bit error. with any change of state of the prbs internal synchronization status an interrupt isr1.llbsc is generated. the current status of the prbs synchronizer is indicated by bit frs1.llbad. the expected prbs sequence has to be selected by bit lcr1.llbp. the prbs status signal is output on pin rfsp ,if x c0.sfr z= 1 and lcr1.eprm = 1. it is set high, if the prbs monitor is in synchronous state. x prbs? transmit pseudo random bit sequence a one in this bit position enables transmitting of a pseudo random bit sequence to the remote end. depending on pit llbp the prbs is generated according to 2 15 -1 or 2 20 -1 ( it u -t o. 151). ldc1?0... length deactivate (down) code these bits defines the length of the llb deactivate code which is programmable in register lcr2. 00? length: 5 bit 01? length: 6 bit 10? length: 7 bit 11? length: 8 bit if a shorter pattern length is required, select a multiple of the required length and repeat the pattern in lcr2. 70 lcr1 eprm x prbs ldc1 ldc0 lac1 lac0 fllb llbp (3 9 )
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 2 98 2000-07 lac1?0... length activate (up) code these bits defines the length of the llb activate code which is programmable in register lcr3. 00? length: 5 bit 01? length: 6 bit 10? length: 7 bit 11? length: 8 bit if a shorter pattern length is required, select a multiple of the required length and repeat the pattern in lcr3. fllb? framed line loopback/invert prbs depending on bit lcr1. x prbs this bit enables different functions: lcr1. x prbs = 0: 0? the line loopback code is transmitted including framing bits. llb code overwrites the fs/dl bits. 1? the line loopback code is transmitted unframed. llb code does not overwrite the fs/dl bits. invert prbs lcr1. x prbs = 1: 0? the generated prbs is transmitted not inverted. 1? the prbs is transmitted inverted. llbp? line loopback pattern lcr1. x prbs = 0 0? fixed line loopback code according to ansi t1. 4 03 (001 = loop down or 00001 = loop up). 1? enable user programmable line loopback code via register lcr2/3. lcr1. x prbs = 1 or lcr1.eprm = 1 0? 2 15 -1 1? 2 20 -1
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 2 99 2000-07 loop code register 2 (read/write) value after reset: 00 h ldc7?ldc0? line loopback deactivate code if enabled by bit fmr5. x ld the llb deactivate code is repeated automatically until the llb generator is stopped. transmit data is overwritten by the llb code. ldc0 is transmitted last. if the selected code length is less than 8 bit, the leftmost bits of lcr2 are ignored. for correct operations bit lcr1. x prbs has to be cleared. loop code register 3 (read/write) value after reset: 00 h lac7?lac0? line loopback activate code if enabled by bit fmr5. x l u the llb activate code is repeated automatically until the llb generator is stopped. transmit data is overwritten by the llb code. lac0 is transmitted last. if the selected code length is less than 8 bit, the leftmost bits of lcr3 are ignored. for correct operations bit lcr1. x prbs has to be cleared. 70 lcr2 ldc7 ldc0 (3a) 70 lcr3 lac7 lac0 (3b)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 300 2000-07 system interface control 1 (read/write) value after reset: 00 h srsc? select receive system clock 0? input frequency on pin scl k r: 8 .1 9 2mhz calculation of delay time t (scl k r cycles) depends on the value x of the ?receive counter offset? register rc1/0 and of the programming of rc0.rcos. delay t is an even number in the range of 0 to 1022: rcos = 0: x= 5 ? t/2 if x= 517 ? t/2 if delay t is an odd number in the range of 1 to 1023: rcos = 1: x= 5 ? (t ? 1)/2 if x= 517 ? (t ? 1)/2 if 1? input frequency on pin scl k r: 1.5 44 mhz calculation of delay time t (scl k r cycles) depends on the value x of the ?receive counter offset? register rc1/0: t = (196-x/2)mod193 delay time t = time between beginning of time-slot 0 at rdo and the initial edge of scl k rafters y pr goes active. if this bit is set fmr1.imod must be set also and bit rc0.0 should be cleared. rbs1?0? receive buffer size 00? buffer size: 2 frames 01? buffer size: 1 frame 10? buffer size: 9 2bits 11? bypass of receive elastic store 70 sic1 srsc rbs1 rbs0 s x sc x bs1 x bs0 (3c) 0t10 ? 12 t 1022 ? 1t11 ? 13 t 1023 ?
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 301 2000-07 s x sc? select transmit system clock 0? input frequency on pin scl kx : 8 .1 9 2mhz calculation of delay time t (scl kx cycles) depends on the value x of the ?transmit counter offset? register x c1/0 and of the programming of x c1. x cos: delay t is an even number in the range of 0 to 1022: x cos = 0: x = 498 -t/2 if x= 1010 - t/2 if delay t is an odd number in the range of 1 to 1023: x cos = 1: x = 498 -(t-1)/2 if x= 1010 - (t-1)/2 if 1? input frequency on pin scl kx :1.5 44 mhz calculation of delay time t (scl kx cycles) depends on the value x of the ?transmit counter offset? register x c1/0: t = (380 ? x/2) mod 193 delay time t = time between beginning of time-slot 0 at x di and the initial edge of scl kx after s y p x goes active. if this bit is set fmr1.imod must be set also and bit x c0.0 should be cleared. x bs1?0? transmit buffer size 00? by-pass of transmit elastic store (scl kx= 1.5 44 mhz) or 1 frame (scl kx = 8 .1 9 2mhz) 01? buffer size: 1 frame 10? buffer size: 2 frames 11? buffer size: 9 2bits system interface control 2 (read/write) value after reset: 00 h ffs? force freeze signaling setting this bit disables updating of the receive signaling buffer and current signaling information is frozen. after resetting this bit and receiving a complete superframe updating of the signaling buffer is 70 sic2 ffs ssf srfso (3d) 0t 99 6 ? 9 98 t 1022 ? 1t 99 7 ? 9 99 t 1023 ?
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 302 2000-07 started again. the freeze signaling status could be also automatically generated by detecting the loss of signal alarm or a loss of frame alignment or a receive slip (only if external register access via rsig is enabled). this automatic freeze signaling function is logically ored with this bit. the current internal freeze signaling status is available in register sis.sfs. ssf? serial signaling format only applicable if pin function r/ x sig is selected. 0? bits 1... 4 in all time-slots except time-slot 0 + 16 are cleared. 1? bits 1... 4 in all time-slots except time-slot 0 + 16 are set high. srfso? select receive frame sync output 0? pin s y pr : input 1? pin s y pr : output setting this bit disables the timeslot assigner. with register rc1/0 the receive frame marker could be activated during any bit position of the current frame. this marker is active high for one 1.5 44 -mhz cycle and is clocked off with the falling edge of scl k r or rcl k if the receive elastic store is bypassed. if no s y pr has been activated since reset or software reset cmdr.res the outputs of the receive system interface assumes an arbitrary alignment. calculation of the value x of the ?receive counter offset? register rc1/0 depends on scl k r and on the bit position bp which should be marked: x= (2bp) mod 386 ,forscl k r = 1.5 44 mhz line interface mode 3 (read/write) value after reset: 00 h csc? configure system clock cl k 16m/cl k 12m 0? dejittered x tal1 or x tal3 clock is output on cl k 16m/ cl k 12m. 1? buffered x tal1 or x tal3 clock is output on cl k 16m/ cl k 12m. 70 lim3 csc es y (3e)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 303 2000-07 esy? external synchronization of dco2 together with bit loop.spn the functionality of pin 8 0 is defined: programming of loop.spn and lim3.es y and the corresponding pin function is shown below. spn/es y : 00? function of pin 8 0 x sig: if sic3.ttrf = 1, transmit data from the system interface. no input function defined for sic3.ttrf = 0. 01? function of pin 8 0s y nc2: external synchronization input for the dco- x circuitry. 10? function of pin 8 0 roid: receive optical interface data. 11? function of pin 8 0 x sig: transmit signaling input from the transmit system interface. system interface control 3(read/write) value after reset: 00 h ttrf? ttr register function setting this bit the function of the ttr1... 4 registers are changed. a one in each ttr register forces the x sigm marker high for the respective time slot and controls sampling of the time slots provided by pin x sig. x sig is selected by loop.spn = 0 and lim3.es y= 0. daf? disable automatic freeze significant only if the serial signaling access is enabled. 0? signaling is automatically frozen if one of the following alarms occurred: loss of signal (frs0.los), loss of frame alignment (frs0.lfa), or receive slips (isr3.rsp/n). 1? automatic freezing of signaling data is disabled. u pdating of the signaling buffer is also done if one of the above described alarm conditions is active. however, updating of the signaling buffer is stopped if sic2.ffs is set. 70 sic3 ttrf daf ( 4 0)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 30 4 2000-07 disable error counter (write) value after reset: 00 h dbec? disable prbs bit error counter only valid if lcr1.eprm = 1 and fmr1.ecm are reset. dcec? disable crc error counter debc? disable errored block counter dcvc? disable code violation counter dfec? disable framing error counter these bits are only valid if fmr1.ecm is cleared. they have to be set before reading the error counters. they are reset automatically if the corresponding error counter high byte has been read. with the rising edge of these bits the error counters are latched and then cleared. 70 dec dbec dcec debc dcvc dfec (60)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 305 2000-07 transmit signaling registers (write) value after reset: not defined fmr5.sro = 0, fmr5.srs = 1 70 x s1 a 8 a7 a6 a5 a 4 a3 a2 a1 (70) x s2 a16 a15 a1 4 a13 a12 a11 a10 a 9 (71) x s3 a2 4 a23 a22 a21 a20 a1 9 a1 8 a17 (72) x s 4 b 8 b7 b6 b5 b 4 b3 b2 b1 (73) x s5 b16 b15 b1 4 b13 b12 b11 b10 b 9 (7 4 ) x s6 b2 4 b23 b22 b21 b20 b1 9 b1 8 b17 (75) x s7 a/c 8 a/c7 a/c6 a/c5 a/c 4 a/c3 a/c2 a/c1 (76) x s 8 a/c16 a/c15 a/c1 4 a/c13 a/c12 a/c11 a/c10 a/c 9 (77) x s 9 a/c2 4 a/c23 a/c22 a/c21 a/c20 a/c1 9 a/c1 8 a/c17 (7 8 ) x s10 b/d 8 b/d7 b/d6 b/d5 b/d 4 b/d3 b/d2 b/d1 (7 9 ) x s11 b/d16 b/d15 b/d1 4 b/d13 b/d12 b/d11 b/d10 b/d 9 (7a) x s12 b/d2 4 b/d23 b/d22 b/d21 b/d20 b/d1 9 b/d1 8 b/d17 (7b) fmr5.sro = 1, fmr5.srs = 1 70 x s1 a1 b1 c1/a2 d1/b2 a2/a3 b2/b3 c2/a 4 d2/b 4 (70) x s2 a3/a5 b3/b5 c3/a6 d3/b6 a 4 /a7 b 4 /b7 c 4 /a 8 d 4 /b 8 (71) x s3 a5/a 9 b5/b 9 c5/a10 d5/b10 a6/a11 b6/b11 c6/a12 d6/b12 (72) x s 4 a7/a13 b7/b13 c7/a1 4 d7/b1 4 a 8 /a15 b 8 /b15 c 8 /a16 d 8 /b16 (73) x s5 a 9 /a17 b 9 /b17 c 9 /a1 8 d 9 /b1 8 a10/a1 9 b10/b1 9 c10/a20 d10/b20 (7 4 ) x s6 a11/a21 b11/b21 c11/a22 d11/b22 a12/a23 b12/b23 c12/a2 4 d12/b2 4 (75) x s7 a13/a1 b13/b1 c13/a2 d13/b2 a1 4 /a3 b1 4 /b3 c1 4 /a 4 d1 4 /b 4 (76) x s 8 a15/a5 b15/b5 c15/a6 d15/b6 a16/a7 b16/b7 c16/a 8 d16/b 8 (77) x s 9 a17/a 9 b17/b 9 c17/a10 d17/b10 a1 8 /a11 b1 8 /b11 c1 8 /a12 d1 8 /b12 (7 8 ) x s10 a1 9 /a13 b1 9 /b13 c1 9 /a1 4 d1 9 /b1 4 a20/a15 b20/b15 c20/a16 d20/b16 (7 9 ) x s11 a21/a17 b21/b17 c21/a1 8 d21/b1 8 a22/a1 9 b22/b1 9 c22/a20 d22/b20 (7a) x s12 a23/a21 b23/b21 c23/a22 d23/b22 a2 4 /a23 b2 4 /b23 c2 4 /a2 4 d2 4 /b2 4 (7b)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 306 2000-07 transmit signaling register 1...12 the transmit signaling register access is enabled by setting bit fmr5.eibr = 1. each register contains the bit-robbing information for 8 ds0 channels. starting with x mb (transmit multiframe begin), the contents of these registers is copied into a shadow register bank. u pon completion, cas empty interrupt isr1.case is set. the contents of the shadow registers is sent out subsequently in the corresponding bit positions of the next outgoing multiframe. the transmit cas empty interrupt isr1.case requests that these registers should be serviced within the next 3 ms before the next multiframe begin. if requests for new information are ignored, current contents is repeated. if access to x s1...12 registers is done without control of the interrupt isr1.case and the write access to these registers is done exact in that moment when this interrupt is generated, data may be lost. note: a software reset (cmdr.xres) resets these registers.
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 307 2000-07 10.3 t1/j1 status register addresses table 55 t1/j1 status register address arrangement address register type comment page 00 rfifo r receive fifo 309 01 rfifo r receive fifo 309 4 b res r receive equalizer status 309 4 c frs0 r framer receive status 0 310 4 d frs1 r framer receive status 1 312 4 e frs2 r framer receive status 2 314 4 f frs3 r framer receive status 3 315 50 fecl r framing error counter low 316 51 fech r framing error counter high 316 52 cvcl r code violation counter low 317 53 cvch r code violation counter high 317 5 4 cecl r crc error counter low 318 55 cech r crc error counter high 318 56 ebcl r errored block counter low 319 57 ebch r errored block counter high 319 5 8 becl r bit error counter low 320 5 9 bech r bit error counter high 320 5c rdl1 r receive dl-bit register 1 321 5d rdl2 r receive dl-bit register 2 321 5e rdl3 r receive dl-bit register 3 321 6 4 sis r signaling status register 322 65 rsis r receive signaling status register 323 66 rbcl r receive byte control low 325 67 rbch r receive byte control high 325 6 8 isr0 r interrupt status register 0 325 6 9 isr1 r interrupt status register 1 327 6a isr2 r interrupt status register 2 328 6b isr3 r interrupt status register 3 330 6c isr5 r interrupt status register 5 331
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 30 8 2000-07 6e gis r global interrupt status 332 6f vstr r version status 332 70 rs1 r receive signaling register 1 333 71 rs2 r receive signaling register 2 333 72 rs3 r receive signaling register 3 333 73 rs 4 r receive signaling register 4 333 7 4 rs5 r receive signaling register 5 333 75 rs6 r receive signaling register 6 333 76 rs7 r receive signaling register 7 333 77 rs 8 r receive signaling register 8 333 7 8 rs 9 r receive signaling register 9 333 7 9 rs10 r receive signaling register 10 333 7a rs11 r receive signaling register 11 333 7b rs12 r receive signaling register 12 333 table 55 t1/j1 status register address arrangement (cont?d) address register type comment page
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 30 9 2000-07 10.4 detailed description of t1/j1 status registers receive fifo (read) reading data from rfifo can be done in an 8 -bit (byte) or 16-bit (word) access depending on the selected bus interface mode. the lsb is received first from the serial interface. the size of the accessible part of rfifo is determined by programming the bits ccr1.rft1 0 (rfifo threshold level). it can be reduced from 32 bytes (reset value) down to 2 bytes (four values: 32, 16, 4 ,2bytes). data transfer u p to 32 bytes/16 words of received data can be read from the rfifo following a rpf or a rme interrupt. rpf interrupt: a fixed number of bytes/words to be read (32, 16, 4 ,2bytes).the message is not yet complete. rme interrupt: the message is completely received. the number of valid bytes is determined by reading the rbcl, rbch registers. rfifo is released by issuing the ?receive message complete? command (rmc). receive equalizer status (read) ev1?0... equalizer status valid these bits informs the user about the current state of the receive equalization network. only valid if lim1.e q on is set. 00? equalizer status not valid, still adapting 01? equalizer status valid 10? equalizer status not valid 11? equalizer status valid but high noise floor 70 rfifo rf7 rf0 (00/01) 70 res ev1 ev0 res 4 res3 res2 res1 res0 ( 4 b)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 310 2000-07 res4?0... receive equalizer status the current line attenuation status in steps of about 1. 4 db are displayed in these bits. only valid if bits ev1/0 = 01 and lim1.e q on = 1. accuracy: + /- 2 digit, based on temperature influence and noise amplitude variations. 00000? attenuation: 0 db ... 11001? max. attenuation: -36 db framer receive status register 0 (read) los? loss of signal (red alarm) detection: this bit is set when the incoming signal has ?no transitions? (analog interface) or logical zeros (dig. interface) in a time interval of t consecutive pulses, where t is programmable via pcd register: total account of consecutive pulses: 16 < t <4 0 9 6. analog interface: the receive signal level where ?no transition? is declared is defined by the programmed value of lim1.ril2...0. recovery: analog interface: the bit is reset in short haul mode when the incoming signal has transitions with signal levels greater than the programmed receive input level (lim1.ril2...0) for at least m pulse periods defined by register pcr in the pcd time interval. in long haul mode additionally bit res.6 must be set for at least 250 sec. digital interface: the bit is reset when the incoming data stream contains at least m ones defined by register pcr in the pcd time interval. with the rising edge of this bit an interrupt status bit (isr2.los) is set. for additionally recovery conditions refer also to register lim2.los1. the bit is set during alarm simulation and reset if frs2.esc = 0, 3, 4 , 6,7 and no alarm condition exists. 70 frs0 los ais lfa rra lmfa fsrf ( 4 c)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 311 2000-07 ais? alarm indication signal (blue alarm) this bit is set when the conditions defined by bit fmr 4 .ais3 are detected. the flag stays active for at least one multiframe. with the rising edge of this bit an interrupt status bit (isr2.ais) is set. it is reset with the beginning of the next following multiframe if no alarm condition is detected. the bit is set during alarm simulation and reset if frs2.esc = 0, 3, 4 , 7 and no alarm condition exists. lfa? loss of frame alignment the flag is set if pulseframe synchronization has been lost. the conditions are specified via bit fmr 4 .ssc1/0. setting this bit causes an interrupt (isr2.lfa). the flag is cleared when synchronization has been regained. additionally interrupt status isr2.far is set with clearing this bit. rra? receive remote alarm (yellow alarm) the flag is set after detecting remote alarm (yellow alarm). conditions for setting/resetting are defined by bit rc0.rram. with the rising edge of this bit an interrupt status bit isr2.ra is set. with the falling edge of this bit an interrupt status bit isr2.rar is set. the bit is set during alarm simulation and reset if frs2.esc = 0, 3, 4 ,5,7 and no alarm condition exists. lmfa? loss of multiframe alignment set in f12 or f72 format when 2 out of 4 -(or 5 or 6) multiframe alignment patterns are incorrect or if lfa (loss of basic frame alignment) is detected. additionally the interrupt status bit isr2.lmfa is set. cleared after multiframe synchronization has been regained. with the falling edge of this bit an interrupt status bit isr2.mfar is generated. fsrf? frame search restart flag toggles when no framing candidate (pulse framing or multiframing) is found and a new frame search is started.
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 312 2000-07 framer receive status register 1 (read) e xz d? excessive z eros detected significant only if excessive zeros detection is enabled (fmr2.e xz e = 1). set after detecting of more than 7 (b 8z s code) or more than 15 (ami code) contiguous zeros in the received bit stream. this bit is cleared when read. pden? pulse density violation detected the pulse density of the received data stream is below the requirement defined by ansi t1. 4 03 or more than 15 consecutive zeros are detected. with the violation of the pulse density this bit is set and remains active until the pulse density requirement is fulfilled for 23 consecutive ?1? pulses. additionally an interrupt status isr0.pden is generated with the rising edge of pden. llbdd? line loop back deactivation signal detected this bit is set in case the llb deactivate signal is detected and then received over a period of more than 33,16 ms with a bit error rate less than 1/100. the bit remains set as long as the bit error rate does not exceed 1/100. if framing is aligned, the first bit position of any frame is not taken into account for the error rate calculation. any change of this bit causes a llbsc interrupt. llbad? line loopback activation signal detected/prbs status depending on bit lcr1.eprm the source of this status bit changed. lcr1.eprm = 0: this bit is set in case the llb activate signal is detected and then received over a period of more than 33,16 ms with a bit error rate less than 1/100. the bit remains set as long as the bit error rate does not exceed 1/100. if framing is aligned, the first bit position of any frame is not taken into account for the error rate calculation. any change of this bit causes a llbsc interrupt. 70 frs1 e xz dpden llbddllbad x ls x lo ( 4 d)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 313 2000-07 prbs status lcr1.eprm = 1: the current status of the prbs synchronizer is indicated in this bit. it is set high if the synchronous state is reached even in the presence of a ber 1/10. a data stream containing all zeros with/without framing bits is also a valid pseudo random bit sequence. the same applies to an all ones data stream, if prbs data inversion is selected. x ls? transmit line short significant only if the ternary line interface is selected by lim1.drs = 0. 0? normal operation. no short is detected. 1? the x l1 and x l2 are shortened for at least 32 pulses. as a reaction of the short the pins x l1 and x l2 are automatically forced into a high impedance state if bit x pm2.da x lt is reset. after 32 consecutive pulse periods the outputs x l1/2 are activated again and the internal transmit current limiter is checked. if a short between x l1/2 is still further active the outputs x l1/2 are in high impedance state again. when the short disappears pins x l1/2 are activated automatically and this bit is reset. with any change of this bit an interrupt isr1. x lsc is generated. in case of x pm2. x lt is set this bit is frozen. pins x l1m and x l2m have to be connected to x l1 and x l2, respectively. x lo? transmit line open 0? normal operation 1? this bit is set if at least 32 consecutive zeros were sent via pins x l1/ x l2 respective x dop/ x don. this bit is reset with the first transmitted pulse. with the rising edge of this bit an interrupt isr1. x lsc is set. in case of x pm2. x lt is set this bit is frozen.
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 31 4 2000-07 framer receive status register 2 (read) esc2?esc0? error simulation counter this three-bit counter is incremented by setting bit fmr0.sim. the state of the counter determines the function to be tested: for complete checking of the alarm indications, eight simulation steps are necessary (frs2.esc = 0 after a complete simulation). some of these alarm indications are simulated only if the falc ? -lh is configured in the appropriate mode. at simulation steps 0, 3, 4 , and 7 pending status flags are reset automatically and clearing of the error counters and interrupt status registers isr0...3 should be done. incrementing the simulation counter should not be done at time intervals shorter than 1.5 ms (f 4 , f12, f72) or 3 ms (esf). otherwise, reactions of initiated simulations may occur at later steps. 70 frs2 esc2 esc1 esc0 ( 4 e) tested alarms esc2 ? 0 = 01234567 lfa x x lmfa x x rra (bit2 = 0) x rra (s-bit frame 12) x rra (dl-pattern) x los x x x ebc (f12,f72) x x ebc (only esf) x x x x ais x x x x fec x x cvc x x x cec (only esf) x x x x slpp x slpn x x slp x x x x
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 315 2000-07 framer receive status register 3 (read) feh5?0? f-bit error history the bits are set if errors occur in the corresponding framing bit locations. they are updated once per superframe (esf format) or every six frames (other framing formats). organization: note:all error history bits corresponding to fs bits substituted by data link information are fixed to ? 0 ? . 70 frs3 feh5 feh 4 feh3 feh2 feh1 feh0 ( 4 f) esf others feh5:fas(2 4 ) ft (6 or 12) feh 4 :fas(20) ft (5 or 11) feh3:fas(16) ft ( 4 or 10) feh2:fas(12) ft (3 or 9 ) feh1:fas( 8 )ft(2or 8 ) feh0:fas( 4 )ft(1or7)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 316 2000-07 framing error counter (read) fe15?0? framing errors this 16-bit counter is incremented when incorrect ft and fs bits in f 4 , f12 and f72 format or incorrect fas bits in esf format are received. framing errors are counted during basic frame synchronous state only (but even if multiframe synchronous state is not reached yet). the error counter doesn?t roll over. during alarm simulation, the counter is incremented twice. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dfec has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.dfec is reset automatically with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. 70 fecl fe7 fe0 (50) 70 fech fe15 fe 8 (51)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 317 2000-07 code violation counter (read) cv15?0? code violations no function if nr z code has been enabled. if the b 8z s code (bit fmr0.rc1/0 = 11) is selected, the 16-bit counter is incremented by detecting violations which are not due to zero substitution. if fmr2.e xz e is set, additionally excessive zero strings (more than 7 contiguous zeros) are detected and counted. if simple ami coding is enabled (fmr0.rc0/1 = 10) all bipolar violations are counted. if fmr2.e xz e is set, additionally excessive zero strings (more than 15 contiguous zeros) are detected and counted. the error counter doesn?t roll over. during alarm simulation, the counter is incremented continuously with every second received bit. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcvc has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.dcvc is reset automatically with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. 70 cvcl cv7 cv0 (52) 70 cvch cv15 cv 8 (53)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 31 8 2000-07 crcerrorcounter(read) cr15?0? crc errors no function if crc6 procedure or esf format are disabled. in esf mode, the 16-bit counter is incremented when a multiframe has been received with a crc error. crc errors are not counted during asynchronous state. the error counter doesn?t roll over. during alarm simulation, the counter is incremented once per multiframe. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcec has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.dcec is reset automatically with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. 70 cecl cr7 cr0 (5 4 ) 70 cech cr15 cr 8 (55)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 31 9 2000-07 errored block counter (read) ebc15?0? errored block counter in esf format this 16-bit counter is incremented once per multiframe if a multiframe has been received with a crc error or an errored frame alignment has been detected. crc and framing errors are not counted during asynchronous state. the error counter doesn?t roll over. in f 4 /12/72 format an errored block contain 4 /12or72frames. incrementing is done once per multiframe if framing errors has been detected. during alarm simulation, the counter is incremented in esf format once per multiframe and in f 4 /12/72 format only one time. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.debc has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.debc is reset automatically with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. 70 ebcl ebc7 ebc0 (56) 70 ebch ebc15 ebc 8 (57)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 320 2000-07 bit error counter (read) bec15?0? bit error counter if the prbs monitor is enabled by lcr1.eprm = 1 this 16-bit counter is incremented with every received prbs bit error in the prbs synchronous state frs1.llbad = 1. the error counter doesn?t roll over. during alarm simulation, the counter is incremented continuously with every second received bit. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the prbs bit error counter bit dec.dbec has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.dbec is reset automatically with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. 70 becl bec7 bec0 (5 8 ) 70 bech bec15 bec 8 (5 9 )
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 321 2000-07 receive dl-bit register 1 (read) rdl17?10? receive dl-bit only valid if f12, f2 4 or f72 format is enabled. the received fs/dl-bits are shifted into this register. rdl10 is received in frame 1 and rdl17 in frame 15, if f2 4 format is enabled. rdl10 is received in frame 26 and rdl17 in frame 4 0, if f72 format is enabled. in f12 format the fs-bits of a complete multiframe is stored in this register. rdl10 is received in frame 2 and rdl15 in frame 12. this register is updated with every receive multiframe begin interrupt isr0.rmb. receive dl-bit register 2 (read) rdl27?20? receive dl-bit only valid if f2 4 or f72 format is enabled. the received dl-bits are shifted into this register. rdl20 is received in frame 17 and rdl23 in frame 23, if f2 4 format is enabled. rdl20 is received in frame 4 2 and rdl27 in frame 56, if f72 format is enabled. this register is updated with every receive multiframe begin interrupt isr0.rmb. receive dl-bit register 3 (read) rdl37?30? receive dl-bit only valid if f72 format is enabled. the received dl-bits are shifted into this register. rdl30 is received in frame 5 8 and rdl37 in frame 72, if f72 format is enabled. 70 rdl1 rdl17 rdl16 rdl15 rdl1 4 rdl13 rdl12 rdl11 rdl10 (5c) 70 rdl2 rdl27 rdl26 rdl25 rdl2 4 rdl23 rdl22 rdl21 rdl20 (5d) 70 rdl3 rdl37 rdl30 (5e)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 322 2000-07 this register is updated with every receive multiframe begin interrupt isr0.rmb. signaling status register (read) x dov? transmit data overflow more than 32 bytes have been written to the x fifo. this bit is reset by: ? a transmitter reset command x res or ? when all bytes in the accessible half of the x fifo have been moved in the inaccessible half. x fw? transmit fifo write enable datacanbewrittentothe x fifo. x rep? transmission repeat status indication of cmdr. x rep. rli? receive line inactive neither flags as interframe time fill nor frames are received via the signaling timeslot. cec? command executing 0 no command is currently executed, the cmdr register can be written to. 1 a command (written previously to cmdr) is currently executed, no further command can be temporarily written in cmdr register. note: cec is active at most 2.5 periods of the current system data rate. sfs? status freeze signaling 0? freeze signaling status inactive. 1? freeze signaling status active. 70 sis x dov x fw x rep rli cec sfs bom (6 4 )
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 323 2000-07 bom? bit oriented message significant only in esf frame format and auto switching mode is enabled. 0? hdlc mode 1? bom mode receive signaling status register (read) rsis relates to the last received hdlc or bom frame ; it is copied into rfifo when end- of-frame is recognized (last byte of each stored frame). vfr? valid frame determines whether a valid frame has been received. 1 valid hdlc frame 0 invalid hdlc frame an invalid frame is either ? a frame which is not an integer number of 8 bits (n 8 bits) in length (e.g.25bits),or ? a frame which is too short taking into account the operation mode selected via mode (mds2...0) and the selection of receive crc on/off (ccr3.rcrc) as follows: mds2...0 = 011 (16 bit address), rcrc = 0: 4 bytes ; rcrc = 1:3- 4 bytes mds2...0 = 010 ( 8 bit address), rcrc = 0:3bytes ; rcrc = 1:2-3bytes note:shorter frames are not reported. rdo? receive data overflow a data overflow has occurred during reception of the frame. additionally, an interrupt can be generated (refer to isr1.rdo/imr1.rdo). crc16? crc16 compare/check 0 crc check failed ; received frame contains errors. 1 crc check o.k. ; received frame is error-free. 70 rsis vfr rdo crc16 rab ha1 ha0 hfr la (65)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 32 4 2000-07 rab? receive message aborted the received frame was aborted from the transmitting station. according to the hdlc protocol, this frame must be discarded by the receiver station. ha1...0? high byte address compare significant only if 2-byte address mode has been selected. in operating modes which provide high byte address recognition, the falc ? -lh compares the high byte of a 2-byte address with the contents of two individually programmable registers (rah1, rah2) and the fixed values fe h and fc h (broadcast address). dependent on the result of this comparison, the following bit combinations are possible (ss7 support not active): 00? rah2 has been recognized 01? broadcast address has been recognized 10? rah1 has been recognized c/r = 0(bit1) 11? rah1 has been recognized c/r = 1(bit1) note: if rah1, rah2 contain identical values, a match is indicated by ? 10 ? or ? 11 ? . hfr ? hdlc frame format 0 a bom frame was received. 1 a hdlc frame was received. note: bits rsis.7...2 and rsis.0 are not valid with a bom frame. this means, if hfr=0, all other bits of rsis have to be ignored la ? low byte address compare significant in hdlc modes only. the low byte address of a 2-byte address field, or the single address byte of a 1-byte address field is compared with two registers. (ral1, ral2). 0 ral2 has been recognized 1 ral1 has been recognized
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 325 2000-07 receive byte count low (read) together with rbch (bits rbc11... 8 ), indicates the length of a received frame (1 4 0 9 5 bytes). bits rbc 4 ...0 indicate the number of valid bytes currently in rfifo. these registers must be read by the cp u following a rme interrupt. received byte count high (read) ov? counter overflow more than 4 0 9 5 bytes received. rbc11...8 receive byte count (most significant bits) together with rbcl (bits rbc7 ... 0) indicate the length of the received frame. interrupt status register 0 (read) value after reset: 00 h all bits are reset when isr0 is read. if bit ipc.vis is set, interrupt statuses in isr0 may be flagged although they are masked via register imr0. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. rme? receive message end one complete message of length less than 32 bytes, or the last part of a frame at least 32 bytes long is stored in the receive fifo, including the status byte. 70 rbcl rbc7 rbc0 (66) 70 rbch ov rbc11 rbc10 rbc 9 rbc 8 (67) 70 isr0 rme rfs isf rmb rsc crc6 pden rpf (6 8 )
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 326 2000-07 the complete message length can be determined reading the rbch, rbcl registers, the number of bytes currently stored in rfifo is given by rbc 4 ...0. additional information is available in the rsis register. rfs? receive frame start this is an early receiver interrupt activated after the start of a valid frame has been detected, i.e. after an address match (in operation modes providing address recognition), or after the opening flag (transparent mode 0) is detected, delayed by two bytes. after an rfs interrupt, the contents of rsis.3...1 is valid and can be read by the cp u . isf? incorrect sync format the falc ? -lh could not detect eight consecutive one?s within 32 bits in bom mode. only valid if bom receiver has been activated. rmb? receive multiframe begin this bit is set with the beginning of a received multiframe of the receive line timing. rsc? received signaling information changed this interrupt bit is set during each multiframe in which signaling information on at least one channel changes its value from the previous multiframe. this interrupt only occurs in the synchronous state. the registers rs1...6/rs1...12 should be read within the next 3 ms otherwise the contents may be lost. crc6? receive crc6 error 0? no crc6 error occurs. 1? the crc6 check of a received multiframe failed. pden? pulse density violation the pulse density violation of the received data stream defined by ansi t1. 4 03 is violated. more than 15 consecutive zeros or less than n ones in each and every time window of 8 (n + 1) data bits (n = 23) are detected. if ipc.sci is set high this interrupt status bit is activated with every change of state of frs1.pden. rpf? receive pool full 32 bytes of a frame have arrived in the receive fifo. the frame is not yet received completely.
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 327 2000-07 interrupt status register 1 (read) all bits are reset when isr1 is read. if bit ipc.vis is set, interrupt statuses in isr1 may be flagged although they are masked via register imr1. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. case? transmit cas register empty in esf format this bit is set with the beginning of a transmitted multiframe related to the internal transmitter timing. in f12 format this bit is set with the beginning of a transmitted multiframe,ifbitfmr5.srs = 0. if fmr5.srs = 1, this bit is set at every second multiframe begin. in f72 format this interrupt occurs every 12/2 4 frames (fmr5.srs = 0/1) to inform the user that new bit-robbing data has to be written to x s1...6 registers (see table 36 " 72-frame multiframe structure (t1/j1) " on page 146 ). rdo? receive data overflow this interrupt status indicates that the cp u did not respond fast enough to an rpf or rme interrupt and that data in rfifo has been lost. even when this interrupt status is generated, the frame continues to be received when space in the rfifo is available again. note:whereas the bit rsis.rdo in the frame status byte indicates whether an overflow occurred when receiving the frame currently accessed in the rfifo, the isr1.rdo interrupt status is generated as soon as an overflow occurs and does not necessarily pertain to the frame currently accessed by the processor. alls? all sent this bit is set if the last bit of the current frame has been sent out completely and x fifo is empty. 70 isr1 case rdo alls x d ux mb x lsc x pr (6 9 )
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 32 8 2000-07 x du? transmit data underrun transmitted frame was terminated with an abort sequence because no data was available for transmission in x fifo and no x me was issued. note: transmitter and xfifo are reset and deactivated if this condition occurs. they are re-activated not before this interrupt status register has been read. thus, xdu should not be masked via register imr1. x mb? transmit multiframe begin this bit is set with the beginning of a transmitted multiframe related to the internal transmit line interface timing. x lsc? transmit line status change x lsc is set with the rising edge of the bit frs1. x lo or with any change of bit frs1. x ls. the actual status of the transmit line monitor can be read from the frs1. x ls and frs1. x lo. x pr? transmit pool ready a data block of up to 32 bytes can be written to the transmit fifo. x pr enables the fastest access to x fifo. it has to be used for transmission of long frames, back-to-back frames or frames with shared flags. interrupt status register 2 (read) all bits are reset when isr2 is read. if bit pic.vis is set, interrupt statuses in isr2 may be flagged although they are masked via register imr2. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. far? frame alignment recovery the framer has reached synchronization. set with the falling edge of bit fsr0.lfa. it is set also after alarm simulation is finished and the receiver is still synchronous. 70 isr2 far lfa mfar lmfa ais los rar ra (6a)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 32 9 2000-07 lfa? loss of frame alignment the framer has lost synchronization and bit frs0.lfa is set. it is set during alarm simulation. mfar? multiframe alignment recovery set when the framer has reached multiframe alignment in f12 or f72 format. with the negative transition of bit frs0.lmfa this bit is set. it is set during alarm simulation. lmfa? loss of multiframe alignment set when the framer has lost the multiframe alignment in f12 or f72 format. with the positive transition of bit frs0.lmfa this bit is set. it is set during alarm simulation. ais? alarm indication signal (blue alarm) this bit is set when an alarm indication signal is detected and bit frs0.ais is set. if ipc.sci is set high this interrupt status bit is activated with every change of state of frs0.ais. it is set during alarm simulation. los? loss of signal (red alarm) this bit is set when a loss of signal alarm is detected in the received data stream and frs0.los is set. if ipc.sci is set high this interrupt status bit is activated with every change of state of frs0.los. it is set during alarm simulation. rar? remote alarm recovery set if a remote alarm (yellow alarm) is cleared and bit frs0.rra is reset. it is set also after alarm simulation is finished and no remote alarm is detected. ra? remote alarm a remote alarm (yellow alarm) is detected. set with the rising edge of bit frs0.rra. it is set during alarm simulation.
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 330 2000-07 interrupt status register 3 (read) all bits are reset when isr3 is read. if bit ipc.vis is set, interrupt statuses in isr3 may be flagged although they are masked via register imr3. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. es? errored second this bit is set if at least one enabled interrupt source via esm is set during the time interval of one second. interrupt sources of esm register: lfa = loss of frame alignment detected fer = framing error received cer = crc error received ais = alarm indication signal (blue alarm) los = loss of signal (red alarm) cve = code violation detected slip = transmit slip or receive slip positive/negative detected sec? second timer the internal one second timer has expired. the timer is derived from clock rcl k . x slp? transmit slip indication only valid if register sic1. x bs1/0 = 01. a one in this bit position indicates that there is an error in the host clock system. if the wander of the transmit route clock, which normally is phase locked to a common submultiple of the system clock (scl kx ), is too great, data transmission errors occur. in that case, the transmit speech memory has to be reset to its start position by writing the initial value to the transmit time-slot counter x c1. x to. llbsc? line loop back status change/prbs status change depending on bit lcr1.eprm the source of this interrupt status changed: lcr1.eprm = 0: this bit is set, if the llb activate signal or the llb deactivate signal respective is detected over a period of 33,16 ms with a bit error rate less than 1/100. 70 isr3 es sec x slp llbsc rsn rsp (6b)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 331 2000-07 the llbsc bit is also set, if the current detection status is left, i.e., if the bit error rate exceeds 1/100. the actual detection status can be read from the frs1.llbad and frs1.llbdd, respectively. prbs status change lcr1.eprm = 1: with any change of state of the prbs synchronizer this bit is set. the current status of the prbs synchronizer is indicated in frs1.llbad. rsn? receive slip negative the frequency of the receive route clock is greater than the frequency of the receive system interface working clock based on 1.5 44 mhz. it is set during alarm simulation. in 2-frame buffer mode a frame is skipped. rsp? receive slip positive the frequency of the receive route clock is less than the frequency of the receive system interface working clock based on 1.5 44 mhz. it is set during alarm simulation. in 2-frame buffer mode a frame is repeated. interrupt status register 4 (read) all bits are reset when isr5 is read. if bit ipc.vis is set, interrupt statuses in isr5 may be flagged although they are masked via register imr5. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. x sp? transmit slip positive the frequency of the transmit clock is less than the frequency of the transmit system interface working clock based on 1.5 44 mhz. after a slip has performed writing of register x c1 is not necessary. in 2-frame buffer mode a frame is repeated. 70 isr5 x sp x sn (6c)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 332 2000-07 x sn? transmit slip negative the frequency of the transmit clock is greater than the frequency of the transmit system interface working clock based on 1.5 44 mhz. after a slip has performed writing of register x c1 is not necessary. in 2-frame buffer mode a frame is skipped. global interrupt status register (read) value after reset: 00 h this status register points to pending interrupts sourced by isr5, 3...0. version status register (read) vn7...0? version number of chip 10 h ?version 1.1 13 h ?version 1.3 70 gis isr5 isr3 isr2 isr1 isr0 (6e) 70 vstr vn7 vn0 (6f)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 333 2000-07 receive signaling registers (read) value after reset: not defined fmr5.sro = 0 70 rs1 a 8 a7 a6 a5 a 4 a3 a2 a1 (70) rs2 a16 a15 a1 4 a13 a12 a11 a10 a 9 (71) rs3 a2 4 a23 a22 a21 a20 a1 9 a1 8 a17 (72) rs 4 b 8 b7 b6 b5 b 4 b3 b2 b1 (73) rs5 b16 b15 b1 4 b13 b12 b11 b10 b 9 (7 4 ) rs6 b2 4 b23 b22 b21 b20 b1 9 b1 8 b17 (75) rs7 a/c 8 a/c7 a/c6 a/c5 a/c 4 a/c3 a/c2 a/c1 (76) rs 8 a/c16 a/c15 a/c1 4 a/c13 a/c12 a/c11 a/c10 a/c 9 (77) rs 9 a/c2 4 a/c23 a/c22 a/c21 a/c20 a/c1 9 a/c1 8 a/c17 (7 8 ) rs10 b/d 8 b/d7 b/d6 b/d5 b/d 4 b/d3 b/d2 b/d1 (7 9 ) rs11 b/d16 b/d15 b/d1 4 b/d13 b/d12 b/d11 b/d10 b/d 9 (7a) rs12 b/d2 4 b/d23 b/d22 b/d21 b/d20 b/d1 9 b/d1 8 b/d17 (7b) fmr5.sro = 1 70 rs1 a1 b1 c1/a2 d1/b2 a2/a3 b2/b3 c2/a 4 d2/b 4 (70) rs2 a3/a5 b3/b5 c3/a6 d3/b6 a 4 /a7 b 4 /b7 c 4 /a 8 d 4 /b 8 (71) rs3 a5/a 9 b5/b 9 c5/a10 d5/b10 a6/a11 b6/b11 c6/a12 d6/b12 (72) rs 4 a7/a13 b7/b13 c7/a1 4 d7/b1 4 a 8 /a15 b 8 /b15 c 8 /a16 d 8 /b16 (73) rs5 a 9 /a17 b 9 /b17 c 9 /a1 8 d 9 /b1 8 a10/a1 9 b10/b1 9 c10/a20 d10/b20 (7 4 ) rs6 a11/a21 b11/b21 c11/a22 d11/b22 a12/a23 b12/b23 c12/a2 4 d12/b2 4 (75) rs7 a13/a1 b13/b1 c13/a2 d13/b2 a1 4 /a3 b1 4 /b3 c1 4 /a 4 d1 4 /b 4 (76) rs 8 a15/a5 b15/b5 c15/a6 d15/b6 a16/a7 b16/b7 c16/a 8 d16/b 8 (77) rs 9 a17/a 9 b17/b 9 c17/a10 d17/b10 a1 8 /a11 b1 8 /b11 c1 8 /a12 d1 8 /b12 (7 8 ) rs10 a1 9 /a13 b1 9 /b13 c1 9 /a1 4 d1 9 /b1 4 a20/a15 b20/b15 c20/a16 d20/b16 (7 9 ) rs11 a21/a17 b21/b17 c21/a1 8 d21/b1 8 a22/a1 9 b22/b1 9 c22/a20 d22/b20 (7a) rs12 a23/a21 b23/b21 c23/a22 d23/b22 a2 4 /a23 b2 4 /b23 c2 4 /a2 4 d2 4 /b2 4 (7b)
peb 2255 falc-lh v1.3 t1/j1 registers data sheet 33 4 2000-07 receive signaling register 1...12 each register contains the received bit-robbing information for 8 ds0 channels. the received robbed-bit signaling information of a complete esf multiframe is compared with the previously received one. in f12/72 frame format the received signaling information of every 2 4 frames are compared with the previously received 2 4 frames. if the contents changed a receive signaling change interrupt isr0.rsc is generated and informs the user that a new multiframe has to be read within the next 3 ms. received data is stored in registers rs1...12. rs1.7 is received in channel 1 frame 1 and rs12.0 in channel 2 4 frame 2 4 (esf). if requests for reading the rs1...12 registers is ignored the received data may be lost. additionally a receive signaling data change pointer indicates an update of register rs1...12. refer also to register rsp1/2. access to rs1...12 registers is only valid if the serial receive signaling access on the system highway is disabled.
peb 2255 falc-lh v1.3 electrical characteristics data sheet 335 2000-07 11 electrical characteristics 11.1 absolute maximum ratings note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 11.2 operating range note: in the operating range, the functions given in the circuit description are fulfilled. v dd ,v ddr and v ddx have to be connected to the same voltage level, v ss ,v ssr and v ssx have to be connected to ground level. table 56 maximum ratings parameter symbol limit values unit ambient temperature under bias t a ? 4 0to 8 5 c storage temperature t stg ?65to150 c ic supply voltage (digital) v dd ?0. 4 to 6.5 v ic supply voltage receive (analog) v ddr ?0. 4 to 6.5 v ic supply voltage transmit (analog) v dd x ?0. 4 to 6.5 v voltage on any pin with respect to ground v s ?0. 4 to 6.5 v esd robustness 1) hbm: 1.5 k ? , 100 pf 1) according to mil-std 88 3d, method 3015.7 and esd ass. standard eos/esd-5.1-1 99 3. v esd,hbm 1000 v table 57 power supply range parameter symbol limit values unit test condition min. max. ambient temperature t a - 4 0 8 5 c supply voltages v dd v ddr v dd x 4 .75 5.25 v 1) 1) voltage ripple on analog supply less than 50 mv ground v ss v ssr v ss x 00v
peb 2255 falc-lh v1.3 electrical characteristics data sheet 336 2000-07 11.3 dc characteristics table 58 dc parameters parameter symbol limit values unit notes min. max. input low voltage v il ?0. 4 0. 8 v 1) input high voltage v ih 2.0 v dd + 0. 4 v 1) output low voltage v ol 0. 4 5v i ol =+ 2ma 1) output high voltage v oh1 2. 4 v i oh = - 4 00 a 1) v oh2 v dd -0.5 v i oh = - 100 a 1) input low voltage x tal v x talil ?0. 4 1.0 v input high voltage x tal v x talih 3.5 v dd + 0. 4 v average power supply current (analog line interface) i dde1 i ddt1 165 165 ma ma e1 application 2) t1 application 3) average power supply current (digital line interface) i dd 8 5ma input leakage current i il11 1 a v in =v dd 4 ) i il12 1 a v in =v ss 4 ) i il21 1 a v in =v dd 5) i il12 250 a v in =v ss 5) i il x 15 a v ss < v in peb 2255 falc-lh v1.3 electrical characteristics data sheet 337 2000-07 transmitter output current i x e1 60 ma x l1, x l2 ;x lhp = 0 i x t1 75 ma x l1, x l2 ;x lhp = 1 differential peak voltage of amark (between x l1 and x l2) v x 03.6v transmit line monitor level v x m 0.5 1 v voltage between x l1m and x l2m receiver differential peak voltage of a mark (between rl1 and rl2) v r v dd + 5 % vrl1,rl2 receiver input impedance z r 50 (typical value) k ? 6) receiver sensitivity s rsh 010dbrl1,rl2 lim0.e q on = 0 (short haul) receiver sensitivity s rlhe1 0 4 3dbrl1,rl2 lim0.e q on = 1 (e1, long haul) receiver sensitivity s rlht1 036dbrl1,rl2 lim0.e q on = 1(t1, long haul) receiver input threshold v rth 55 (typical value) % 6) loss of signal (los) detection limit in short haul mode v lossh 1.2 1.0 0. 8 0.5 0. 4 0.2 not assigned not assigned (typical values) v ril2-0 = 000 ril2-0 = 001 ril2-0 = 010 ril2-0 = 011 ril2-0 = 100 ril2-0 = 101 ril2-0 = 110 ril2-0 = 111 7) 1) applies to all pins except analog pins rlx, x lx, x talx, x lmx 2) wiring conditions and external circuit configuration according to figure 23 on page 79 ; values of registers x pm2-0 = bd h ,03 h ,00 h table 58 dc parameters (cont?d) parameter symbol limit values unit notes min. max.
peb 2255 falc-lh v1.3 electrical characteristics data sheet 33 8 2000-07 note: typical characteristics specify mean values expected over the production spread. if not specified otherwise, typical characteristics apply at t a =25 c and 5.0v supply voltage. 3) wiring conditions and external circuit configuration according to figure 49 on page 134 ; values of registers x pm2-0 =9 f h ,27 h ,02 h 4 ) applies to all pins except rcl k ,s y nc, tdi, tms, tc k , rl1, rl2, x l1, x l2 5) applies to pins s y nc, tdi, tms, tc k only 6) parameter not tested in production 7) differential input voltage between pins rl1 and rl2 ; depends on programming of register lim1.ril2-0
peb 2255 falc-lh v1.3 electrical characteristics data sheet 33 9 2000-07 11.4 ac characteristics 11.4.1 recommended oscillator circuits figure 61 crystal oscillator circuit (master/slave mode) figure 62 external oscillator circuit (master mode) 11.4.2 x tal clock timing figure 63 x tal external clock timing table 59 x tal timing parameter values no. parameter limit values unit condition min. typ. max. 61 clock period 61 ns x tal1, x tal3 8 1 x tal3 x tal1(3) x tal2( 4 ) c l t1: 16.3 84 (12.352) mhz e1: 16.3 84 mhz c l f0032 x tal1(3) x tal2( 4 ) external oscillator signal t1: 16.3 84 (12.352) mhz e1: 16.3 84 mhz n.c. f0033 itt06478 xtal3 62 61 xtal1 3.5 v 0.8 v 63
peb 2255 falc-lh v1.3 electrical characteristics data sheet 3 4 0 2000-07 figure 64 external pullable crystal tuning range note: 12.352-mhz or 16.384-mhz crystal specified for c l =15 pf 62 clock high phase 20 ns x tal1, x tal3 25 x tal3 63 clock low phase 20 ns x tal1, x tal3 25 x tal3 clock accuracy 32 1) ppm x tal1, x tal3 motional capacitance c 1 25 ff x tal1, x tal3 shunt capacitance c 0 7pf x tal1, x tal3 load capacitance c l 2) 15 pf x tal1, x tal3 resonance resistance r r 4 0 ? x tal1, x tal3 1) to fulfill e1/t1/j1 requirements in free running mode 2) this value includes the capacitance of the external capacitor plus all parasitic capacitances. the value for the external capacitor has to be chosen depending on the printed circuit board layout. a typical value is 10 pf with 5 pf parasitic capacitance. table 59 x tal timing parameter values (cont?d) no. parameter limit values unit condition min. typ. max. itd08571 7.5 -250 load capacitance 0 f f 0 f - -200 -150 -100 -50 0 50 100 150 ppm 250 10 12.5 15 17.5 20 22.5 pf 27.5
peb 2255 falc-lh v1.3 electrical characteristics data sheet 3 4 1 2000-07 11.4.3 jtag boundary scan interface figure 65 jtag boundary scan timing identification register : 32 bit ; version: 4 h ; part number: 4 2 h , manufacturer: 0 8 3 h table 60 jtag boundary scan timing parameter values no. parameter limit values unit min. max. 8 0tc k period 250 ns 8 1tc k high time 8 0ns 8 2tc k low time 8 0ns 8 3tmssetuptime 4 0ns 84 tms hold time 4 0ns 8 5tdisetuptime 4 0ns 8 6 tdi hold time 4 0ns 8 7 tdo valid delay 100 ns itt06481 81 82 80 tck tms tdo tdi 84 83 85 86 87
peb 2255 falc-lh v1.3 electrical characteristics data sheet 3 4 2 2000-07 11.4.4 reset figure 66 reset timing 11.4.5 microprocessor interface 11.4.5.1 intel bus interface mode figure 67 intel non-multiplexed address timing table 61 reset timing parameter values no. parameter limit values unit min. max. 88 res pulse width high 20 1) 1) after power supply and input clocks are stable s res 88 f0035 wr rd cs ... bhe a6 a0 1 3 2 3a itt06468
peb 2255 falc-lh v1.3 electrical characteristics data sheet 3 4 3 2000-07 figure 68 intel multiplexed address timing figure 69 intel read cycle timing wr rd 3 cs ale bhe a6 ... a0 4 6 1 7 5 3a itt06469 7a cs itt06470 rd 8 9 12 wr float float 11 11a 10 d0 ... (d15...d8) d7
peb 2255 falc-lh v1.3 electrical characteristics data sheet 3 44 2000-07 figure 70 intel write cycle timing table 62 intel bus interface timing parameter values no. parameter limit values unit min. max. 1 address ax 1) ,bhe setup time 15 ns 2 address ax 1) ,bhe hold time 0 ns 3cs setup time 0 ns 3a cs hold time 0 ns 4 address, bhe stable before ale inactive 20 ns 5 address, bhe hold after ale inactive 10 ns 6 ale pulse width 30 ns 7 address latch setup time before command active 0ns 7a ale to command inactive delay 30 ns 8 rd pulse width 100 ns 9 rd control interval 8 0ns 10 data valid after rd active 9 5ns 11 data hold after rd inactive 10 ns 11a rd inactive to data bus tristate 2) 30 ns 12 wr to rd or rd to wr control interval 8 0ns 13 wr pulse width 60 ns 1 4 wr control interval 50 ns d8) d7 d0 ... (d15... 16 itt06471 wr rd cs 15 13 14 12
peb 2255 falc-lh v1.3 electrical characteristics data sheet 3 4 5 2000-07 11.4.5.2 motorola bus interface mode figure 71 motorola read cycle timing 15 data stable before wr inactive 30 ns 16 data hold after wr inactive 10 ns 1) ax refers to address lines a0 to a6 2) typical value, not tested in production table 62 intel bus interface timing parameter values (cont?d) no. parameter limit values unit min. max. ble a6 17 19 18 19a 22 23 21 20 cs rw ds d7 (d15 itt06472 25 24 25a float float ... ... ... a0 d0 d8)
peb 2255 falc-lh v1.3 electrical characteristics data sheet 3 4 6 2000-07 figure 72 motorola write cycle timing table 63 motorola bus interface timing parameter values no. parameter limit values unit min. max. 17 address, ble , setup time before ds active 15 ns 1 8 address, ble , hold after ds inactive 0 ns 1 9 cs active before ds active 0 ns 1 9 acs hold after ds inactive 0 ns 20 rw stable before ds active 10 ns 21 rw hold after ds inactive 0 ns 22 ds pulse width (read access) 100 ns 22a ds pulse width (write access) 60 ns 23 ds control interval 8 0ns 2 4 data valid after ds active (read access) 9 5ns 25 data hold after ds inactive (read access) 10 ns 25a ds inactive to databus tristate (read access) 1) 1) typical value, not tested in production 30 ns 26 data stable before ds active (write access) 30 ns 27 data hold after ds inactive (write access) 10 ns ds ... d0 (d15 d7... d8) 26 rw cs a0 a6 bhe ... 20 19 17 22a 27 itt06473 21 19a 18 23
peb 2255 falc-lh v1.3 electrical characteristics data sheet 3 4 7 2000-07 11.4.6 line interface figure 73 timing of dual rail optical interface table 64 dual rail optical interface parameter values no. parameter limit values unit e1 t1 min. typ. max. min. typ. max. 30 rcl k i clock period 488 6 48 ns 31 rcl k i clock period low 1 8 02 4 0ns 32 rcl k i clock period high 1 8 02 4 0ns 33 roid setup 50 50 ns 3 4 roid hold 50 50 ns 35 x cl k clock period 488 6 48 ns 36 x cl k clock period low x cl k clock period low 3) 1 9 0 150 230 200 ns 37 x cl k clock period high x cl k clock period high 3) 1 9 0 150 230 200 ns 1t2b coding xdon xdop/ xoid/ xoid 1) 1) 38 38a xclk roid rclki 37 32 35 33 36 34 30 31 itt06475 1) cmi coding
peb 2255 falc-lh v1.3 electrical characteristics data sheet 3 48 2000-07 figure 74 receive clock and rfsp /free z stiming 3 8x oid delay 1) x dop/ x don delay 2) 60 60 ns 1) nr z coding 2) hdb3/ami/b 8z s coding 3) depends on input rcl k i in optical interface and remote loop without transmit jitter attenuator enabled (lim1.jatt/rl = 01). table 65 receive clock and rfsp/free z s timing parameter values no. parameter limit values unit e1 t1 min. typ. max. min. typ. max. 3 9 rcl k clock period 488 6 48 ns 4 0 rcl k clock low 1 8 02 4 0ns 4 1 rcl k clock high 1 8 02 4 0ns table 64 dual rail optical interface parameter values (cont?d) no. parameter limit values unit itt06476 43 43 ~ ~ 42 42 40 41 39 rclk rfsp freezs sclkr 1) pcm24: if bit xco 1) . sfrz is set high cfrz is set high . if bit frm3. pcm30:
peb 2255 falc-lh v1.3 electrical characteristics data sheet 3 49 2000-07 4 2rfsp delay 70 70 ns 4 3free z s delay 1) 9 5 9 5ns 1) t1 using register accessed cas and x co.sfr z= 1ore1/t1/j1usingserialcas table 65 receive clock and rfsp/free z stiming (cont?d) parameter values no. parameter limit values unit e1 t1 min. typ. max. min. typ. max.
peb 2255 falc-lh v1.3 electrical characteristics data sheet 350 2000-07 11.4.7 system interface figure 75 system interface timing xc1 sample edge bit during payload loop is active sclkr is switched internally on sclkx valid in pcm30 mode and valid if fmr2 3) xclk xsigm dlx xmfb 2) 1) 3) sclkr xmfs 8192 sypx xdi khz 2) jatt/rl lim1 . = "00" example: 75 plb . "0" = 76 75 ~ ~ 76 ~ ~ ~ ~ 73 74 "0" "1" rdo fmr1 sclkx rmfb dlr rsigm 1) imod . = rdo fmr1 sypr imod . = 8192 sclkr khz 65 67 72 71 ~ ~ ~ ~ 66 72 ~ ~ ~ ~ ~ ~ 65 67 66 xc0 3e = h 03 = h "1") (fmr2 plb = 68 69 . 70 itt06479 68 70 0 of xdi 71a 69 trigger edge
peb 2255 falc-lh v1.3 electrical characteristics data sheet 351 2000-07 figure 76 x mfs timing figure 77 x mfs timing (cont?d.) table 66 system interface timing parameter values no. parameter limit values unit min. typ. max. 65 scl kx /scl k r period 122 ns 66 scl kx /scl k rlow( 8 .1 9 2mhz) 4 0ns scl kx /scl k rlow(1.5 44 /2.0 48 mhz) 120 ns sclkx data at xdi 2 data at xdi 4 8192 time-slot 1.b 2.b 3.b 4.b 7.b 8.b 1.b 1.b 2.b 3.b 4.b 5.b 6.b 7.b 8.b 1.b xmfs frame itt06480 1 of multiframe 0 time-slot 31 frame 2 mbit/s-mode khz 77 79 78 mbit/s-mode 7 8 77 inactive active high scl kx x mfs 7 9 f0058
peb 2255 falc-lh v1.3 electrical characteristics data sheet 352 2000-07 67 scl kx /scl k rhigh( 8 .1 9 2mhz) 4 0ns scl kx /scl k rhigh(1.5 44 /2.0 48 mhz) 120 ns 6 8 s y p x /s y pr inactive setup time 2 t 65 ns 6 9 s y p x /s y pr setup time 5 ns 70 s y p x /s y pr hold time 50 ns 71 rdo delay 1) 10 105 ns 71a rdo to high impedance 1)2) 10 105 ns 72 rsigm, rmfb, dlr marker delay 105 ns 73 x di setup time 5 ns 7 4x di hold time 50 ns 75 x sigm, x mfb, dl x marker delay 105 ns 76 x cl k delay 105 ns 77 x mfs setup time 5 ns 7 8x mfs hold time 50 ns 7 9x mfs inactive time 1) 4 t 65 ns 1) not tested in production 2) fmr1.imod = 0 table 66 system interface timing parameter values (cont?d) no. parameter limit values unit
peb 2255 falc-lh v1.3 electrical characteristics data sheet 353 2000-07 x figure 78 system clock timing itt10534 clk clkx fsc clk 57 58 59 55 54 53 16m 12m 51 52 50 8m clk 49 48 47 45 44 46 clkx clkx clkx 4) 3) 2) 1) lim0.scl1/0 = "10" 1) 2) lim0.scl1/0 = "11" lim0.scl1/0 = "01" 4) 3) lim0.scl1/0 = "00" lim1.efsc = "1" 5) xclk/fsc 5) 56 56
peb 2255 falc-lh v1.3 electrical characteristics data sheet 35 4 2000-07 table 67 system clock timing parameter values no. parameter limit values unit min. typ. max. 44 cl k 16m period 61 ns 4 5cl k 16m low 20 ns 4 6cl k 16m high 20 ns 4 7cl k8 m period 122 ns 48 cl k8 mlow 4 5ns 49 cl k8 mhigh 4 5ns 50 cl kx period 4 mhz 2 44 ns 51 cl kx low 4 mhz 100 ns 52 cl kx high 4 mhz 100 ns 53 cl kx period2mhz 488 ns 5 4 cl kx low 2 mhz 220 ns 55 cl kx high 2 mhz 220 ns 56 fsc, fsc ,cl k8 m, cl kx delay 50 ns 57 cl k 12m period (t1/j1) 8 1ns cl k 12m period (e1) 61 ns 5 8 cl k 12m low (t1/j1) 25 ns cl k 12m low (e1) 20 ns 5 9 cl k 12m high (t1/j1) 25 ns cl k 12m high (e1) 20 ns
peb 2255 falc-lh v1.3 electrical characteristics data sheet 355 2000-07 11.4.8 pulse templates - transmitter 11.4.8.1 pulse template e1 figure 79 pulse shape at transmitter output for e1 applications itd00573 10 % 10 % % 10 10 % % 10 10 % 20 % 269 ns (244 + 25) (244 - 50) ns 194 219 ns (244 - 25) ns 244 (244 + 244) ns 488 % 0 50 % % v =100 nominal pulse % 20 20 %
peb 2255 falc-lh v1.3 electrical characteristics data sheet 356 2000-07 11.4.8.2 pulse template t1 figure 80 t1 pulse shape table 68 t1 pulse template (ansi t1.102) maximum curve minimum curve time [ns] level [ % ] 1) 1) 100 % value must be in the range of 2. 4 v and 3.6 v ; tested at 0 ft. and 655 ft. time [ns] level [ % ] 050-5 2505350-5 325 8 035050 325 115 4 00 9 5 4 25 115 500 9 5 500 105 600 9 0 675 105 650 50 725 -7 650 - 4 5 1100 5 8 00 - 4 5 1250 5 9 25 -20 1100 -5 1250 -5 itd00574 % 100 = v 50 % 0 -50 % 0 250 500 750 1000 ns t normalized amplitude
peb 2255 falc-lh v1.3 electrical characteristics data sheet 357 2000-07 11.5 capacitances table 69 capacitances parameter symbol limit values unit notes min. max. input capacitance 1) 1) not tested in production. c in 5 10 pf all except x lxm, x talx, refr output capacitance 1) c o u t 8 15 pf all except x lx, x talx output capacitance 1) c o u t 8 20 pf x lx reference voltage blocking capacitance 1) c refr 6 8 0 2) 2) 6 8 0 pf are recommended value for best performance in crystal-less mode. 5000 pf refr only ; including external parasitics 3) 3) external wiring must be as short as possible.
peb 2255 falc-lh v1.3 electrical characteristics data sheet 35 8 2000-07 11.6 package characteristics figure 81 thermal behavior of package table 70 package characteristic values parameter symbol limit values unit notes min. typ. max. thermal resistance r thja 1) 1) r thja = (t junction -t ambient )/power not tested in production. 4 7 k /w single layer pcb, no convection r thjc 2) 2) r thjc = (t junction -t case )/power not tested in production. 9k /w junction temperature r j 125 c f0051
peb 2255 falc-lh v1.3 electrical characteristics data sheet 35 9 2000-07 11.7 test configuration figure 82 input/output waveforms for ac testing typical characteristics are mean values expected over the production spread. if not specified otherwise, typical characteristics apply at t a = 25 c and v dd = 5.0v. table 71 ac test conditions parameter symbol test values unit notes load capacitance c l 50 pf input voltage high v ih 2. 4 v all except rlx.y input voltage low v il 0. 4 v all except rlx.y test voltage high v th 2.0 v all except x lx.y test voltage low v tl 0. 8 v all except x lx.y timing test points v th v tl device under test c l test levels v ih v il drive levels f0067
peb 2255 falc-lh v1.3 package outlines data sheet 360 2000-07 12 package outlines p-mqfp-80-1 (plastic metric q uad flat package) smd = surface mounted device sorts of packing package outlines for tubes, trays etc. are contained in our data book ?package information?. dimensions in mm
peb 2255 falc-lh v1.3 appendix data sheet 361 2000-07 13 appendix 13.1 protection circuitry thedesignin figure 83 is a suggestion how to build up a generic e1/t1/j1 platform which is able to meet protection requirements according to bellcore tr-nwt-10 89 ,fcc part6 8 , u l1 4 5 9 . with the selection of the appropriate components the same circuitry is also able to handle the return loss and impedance to ground requirements of etsi. figure 83 protection circuitry f0129 p00 8 0sa 2xp1 8 00sc r 4 r3 r5 falc ? rl1 rl2 x l1 x l2 p00 8 0sa 2xp1 8 00sc r1 r2 1:1 1:2. 4 f1250t f1250t rj 4 5 f1250t f1250t f0128 f1250t f1250t 2xp1 8 00sc r2 r3 r3 rj 4 5 falc ? rl1 rl2 x l1 x l2 f1250t f1250t 2xp1 8 00sc r1 r1 1:1 1:2. 4 v dd v ss v dd v ss
peb 2255 falc-lh v1.3 appendix data sheet 362 2000-07 13.2 application notes several application notes and technical documentation provide additional information. online access to supporting information is available on the internet page: http://www.infineon.com/falc on the same page you find as well the boundary scan file for falc ? -lh version 1.3 (bsdl file) 13.3 software support the following software package is provided together with the falc ? -lh reference system eas y 2255-r1: e1 and t1 driver functions supporting different etsi and bellcore requirements including hdlc and and cas signaling lapd signaling software fdl signaling software boundary scan file for falc ? -lh v1.3 ibis model for falc ? -lh v1.3 gerber files for eas y 2255-r1 external line front end calculator the ?external line front end calculator? provides an easy method to optimize the external components depending on the selected application type. calculation results are traced an can be stored in a file or printed out for documentation. the tool runs under a win 9 x/nt environment. a screenshot of the program is shown in figure 84 below.
peb 2255 falc-lh v1.3 appendix data sheet 363 2000-07 figure 84 external line frontend calculator f0228
peb 2255 falc-lh v1.3 appendix data sheet 36 4 2000-07 13.4 differences to version peb 2255 v1.1 the main feature improvements are: crystal-less jitter attenuation (optionally) serial cas signaling access on the pcm highway (optionally) additional cas-br register organization (for t1) additional transmit data input for fractional e1/t1/j1 selectable receiver transparent mode additional synchronization mode according to ntt requirements (for j1) external reference clock for dco- x (dco2) circuitry (s y nc2 pin) optional transmit clock sourced by dco-r (dco1) circuitry (for e1) software reset for dco-r and dco- x (dco1 and dco2) enhanced loop-timed mode (optionally) version register code changed from 10 h to 13 h boundary scan version register changed from 1 h to 4 h (same part number) boundary scan file changed due to additional pin functions for a detailed description of differences to the previous version see the actual version of peb 2255 version 1.3/delta sheet. all erratas described in ?peb 2255 version 1.1/errata sheet? have been fixed. erratas described in ?peb 2255 version 1.3/errata sheet? have not been fixed. due to compatibility with future products, the following naming conventions have been changed: ?dco-1? to ?dco-r? and ?dco-2? to ?dco- x ?
peb 2255 falc-lh v1.3 glossary data sheet 365 2000-07 14 glossary a/d analog to digital adc analog to digital converter ais alarm indication signal (blue alarm) agc automatic gain control alos analog loss of signal ami alternate mark inversion ansi american national standards institute atm asynchronous transfer mode a ux p auxiliary pattern b 8z s line coding to avoid too long strings of consecutive ?0? ber bit error rate bfa basic frame alignment bom bit orientated message bellcore bell communications research bpv bipolar violation bsn backward sequence number cas channel associated signaling cas-br channel associated signaling - bit robbing cas-cc channel associated signaling - common channel ccs common channel signaling cmi coded mark inversion code (also known as 1t2b code) cr command/response (special bit in ppr) crc cyclic redundancy check cs u channel service unit cvc code violation counter dco digitally controlled oscillator dl digital loop dpll digitally controlled phase locked loop ds1 digital signal level 1 ea extended address (special bit in ppr)
peb 2255 falc-lh v1.3 glossary data sheet 366 2000-07 esd electrostatic discharge eas y evaluation system for falc products esf extended superframe (f2 4 )format e q equalizer etsi european telecommunication standards institute falc ? framing and line interface component fas frame alignment sequence fcc u s federal communication commission fcs frame check sequence (used in ppr) fis u fill in signaling unit fps framing pattern sequence fsn forward sequence number hbm human body model for esd classification hdb3 high density bipolar of order 3 hdlc high level data link control ibis i/o buffer information specification (ansi/eia-656) ibl in band loop ( = llb) isdn integrated services digital network it u international telecommunications group jatt jitter attenuator jtag joined test action group lapd link access procedure on d-channel lbo line build out lcv line code violation li u line interface unit lfa loss of frame alignment ll local loop llb line loop back ( = ibl) los loss of signal (red alarm) lsb least significant bit lss u link status signaling unit mf multiframe
peb 2255 falc-lh v1.3 glossary data sheet 367 2000-07 msb most significant bit ms u message signaling unit nr z non return to zero signal pdv pulse density violation plb payload loop back pll phase locked loop pm q fp plastic metric quad flat pack (device package) ppr periodical performance report prbs pseudo random binary sequence pt q fp plastic thin metric quad flat pack (device package) rai remote alarm indication (yellow alarm) rl remote loop sapi service access point identifier (special octet in ppr) sf superframe sidactor overvoltage protection device for transmission lines tap test access port tei terminal endpoint identifier (special octet in ppr) u i u nit interval z cs z ero code suppression
peb 2255 falc-lh v1.3 data sheet 36 8 2000-07 index a address bus 25 address latch enable 25 afr 1 9 5 ais 1 9 3, 231, 253, 272, 310, 32 8 ais16 1 9 3, 25 4 ais3 27 9 alarm handling 9 3, 1 48 alarm simulation 101, 157 ale 25 alls 1 9 3, 251, 272, 327 alm 1 9 3 almf 1 9 7 api 1 9 3, 25 4 application notes 362 applications 20, 22 as y4 206 atm 22 a u to 27 9 a ux p231 a x ra 1 9 7, 276 a x s201 b bit oriented message 116, 176 bit robbing 115, 116, 12 9 bom 116, 176, 322 boundary scan 44 , 52, 3 4 1, 362 brac 263 brm 266, 2 8 3 bus high enable 27 bus low enable 27 c cas 66, 6 8 , 76, 115, 116, 12 9 , 161 casc 6 8 ,1 9 3, 2 49 case 272, 327 casen 201 cc 2 4 2 ce 2 4 3 cec 2 4 6, 322 cer 1 9 3, 272 cfr z 210 ch 2 9 0 channel translation mode 113 chip select 25 cla 1 99 ,27 8 clear channel 130, 13 4 ,151 clock and data recovery 55, 103 clock synchronization 33, 3 4 clocking u nit 5 4 cmi 210 cr 2 4 0 crc16 2 4 7, 323 crc 4 1 9 3, 2 49 crc6 1 44 , 272, 27 4 ,325 crci 20 4 ,2 84 crc-multiframe 8 6 crystal connection 32 csc 5 8 , 106, 22 4 , 302 ctm 27 4 cv 23 9 cve 1 9 3, 272 d d 4 137, 1 4 0 daf 22 4 , 303 dais 1 9 7, 276 data bus 25, 26 data bus width 26 data link access 116, 130, 17 8 data link bit receive 35 data link bit transmit 4 1 data strobe 26 da x lt 207, 2 88 dbec 30 4 dcec 225, 30 4 dco-1 36 4 dco-2 36 4 dcoc 2 9 3 dco-r 5 8 ,5 9 dco- x 61 dcvc 225, 30 4
peb 2255 falc-lh v1.3 data sheet 36 9 2000-07 debc 225, 30 4 dfec 225, 30 4 dja1 5 8 , 106, 217, 2 9 5 dja2 217, 2 9 5 dl-channel 116, 130 doubleframe format 8 3 drs 5 4 , 8 0, 102, 21 4 ,2 9 3 e eas y 2255-r1 362 ebe 1 9 3 ebp 201 eclb 1 99 ,27 8 ecm 1 9 5, 27 4 edl 27 4 edl x 266 efsc 21 4 ,2 9 3 eibr 2 8 1 eits 266 elastic buffer 63, 77, 111, 131 elos 213, 2 9 1 elt 61, 217, 2 9 5 ensa 1 9 5 eprm 21 8 ,2 9 7 ept 26 8 e q on 5 4 , 55, 102, 213, 2 9 1 error counter 9 5, 150 es 1 9 3, 25 4 , 272, 330 esc 31 4 esd 335 esf 137, 1 4 2 es y 22 4 , 302 ev 55, 230, 30 9 e x ls 272 e x td 1 9 3 e x tiw 210 e xz d312 e xz e276 f f12 137, 13 8 f2 4 137, 1 4 2 f 4 137, 1 4 0 f72 137, 13 8 ,17 8 falc-lh v1.1 57, 105 far 1 9 3, 253, 272, 32 8 fas 67 feh 315 fer 1 9 3, 272 ffs 223, 301 fifo structure 49 fllb 21 8 ,2 9 7 fm0 27 9 fm1 27 9 fmr0 5 4 , 102 fmr1 67 frame aligner 1 9 frame synchronization pulse 33 framer 8 2, 110, 137 freeze signaling 36 frs 1 9 3, 272 fsrf 310 g gerber files 362 gis 50 h h100 17 ha0 2 4 7, 323 ha1 2 4 7, 323 hdlc 66, 76, 115, 12 9 , 161, 16 9 hfr 323 h-mvip 17 hrac 1 8 5, 263 i ibis model 362 ic 212, 2 9 1 ic0 1 8 6, 265 ic1 1 8 6, 265 idl 20 9 ,2 89 imod 1 9 5, 27 4 in-band loop 9 5, 151 initialization in e1 mode 15 8 initialization in t1 / j1 mode 163
peb 2255 falc-lh v1.3 data sheet 370 2000-07 int 50 interface mode 26 interrupt 27 interrupt interface 50 interrupt status registers 51 ipc 51 isf 272, 325 isr 50, 256, 332 isr0 6 8 isr3 65 itf 266 iwe 8 22 j jatt 21 4 ,2 9 3 jitter 5 8 , 61, 105, 10 9 jitter tolerance 10 8 jtag 44 l la 2 4 7, 323 lac 220, 2 99 lac0 21 8 ,2 9 7 lac1 21 8 ,2 9 7 lapd 66, 76, 115, 12 9 , 362 lbo1 2 9 5 lbo2 2 9 5 ldc 220, 2 99 ldc0 21 8 ,2 9 7 ldc1 21 8 ,2 9 7 lfa 1 9 3, 231, 253, 272, 310, 32 8 lim0 5 4 , 55, 5 8 , 102 lim1 8 0 lim2 5 8 , 61, 106 lim3 5 8 , 106 line build-out 135 line coding 55, 103 line interface 1 8 ,2 8 ,30,3 4 7 line receiver 2 8 ,2 9 ll 213, 2 9 1 llbad 236, 312 llbdd 236, 312 llbp 21 8 ,2 9 7 llbsc 1 9 3, 251, 272, 330 lmfa 231, 272, 310, 32 8 lmfa16 1 9 3, 25 4 local loop 99 ,155 loop 5 4 , 102 los 57, 105, 1 9 3, 231, 253, 272, 310, 32 8 , 337 los1 217, 2 9 5 los2 217, 2 9 5 loss of signal 57, 10 4 m mas 5 8 , 213, 2 9 1 mcsp 276 mds 1 8 5, 263 mfar 1 9 3, 253, 272, 32 8 mfbs 2 8 3 mfcs 1 9 5 microprocessor interface 20, 4 7, 3 4 2 n nmf 231 o ov 2 49 p payload loop 98 ,15 4 pcm2 4 137 pden 272, 312, 325 peb 2255 v1.1 36 4 performance monitoring 88 , 9 3, 1 48 plb 1 9 7, 276 pmod 1 9 5, 27 4 power supply 4 3 prbs monitor status 36 pre 26 8 preamble 172 protection 361 pseudo-random bit sequence 9 7, 152 p-t q fp-1 44 - 8 360 pulse density 152 pulse shaper 8 0, 135
peb 2255 falc-lh v1.3 data sheet 371 2000-07 pulse template 355, 356 r ra 1 9 3, 253, 272, 32 8 ra16 1 9 3, 25 4 rab 2 4 7, 323 radd 26 8 rar 1 9 3, 253, 272, 32 8 rbc 2 48 ,2 49 rbs 6 4 , 112 rbs0 221, 300 rbs1 221, 300 rc 1 9 3 rc0 6 9 , 272 rc1 5 4 , 102, 272 rco0 20 4 ,2 84 rco1 20 4 ,2 84 rco2 20 4 ,2 84 rcos 20 4 ,2 84 rcrc 26 8 rdis 20 4 ,2 84 rdl3t1 321 rdo 1 9 3, 2 4 7, 251, 272, 323, 327 read enable 26 read/write enable 26 receive clock 3 4 receive clock input 2 9 receive data input negative 2 9 receive data input positive 2 8 receivedataout35 receive equalization network 55, 103 receive frame marker 37 receive frame synchronous pulse 36 receive line attenuation indication 55, 103 receive line interface 5 4 ,102 receive multiframe begin 3 8 receive optical interface data 2 8 receive signaling data 35 receive signaling marker 3 8 receiver configuration 56 reference resistance 44 reference system 362 register addresses 1 8 0, 22 8 ,25 8 , 307 remote alarm 1 44 remote loop 9 7, 153 res 55 reset 4 3, 15 8 , 163, 3 4 2 rfifo 4 7 rfs 1 9 3, 2 49 , 272, 325 rfs0 1 9 7 rfs1 1 9 7 rft0 266 rft1 266 ril 21 4 ,2 9 3 rl 21 4 ,2 9 3 rli 2 4 6, 322 rmb 1 9 3, 2 49 , 272, 325 rmc 1 8 3, 261 rme 1 9 3, 2 49 , 272, 325 rpf 1 9 3, 2 49 , 272, 325 rra 231, 236, 310 rram 2 8 6 rres 1 8 3, 261 rs13 236 rs15 236 rsc 272, 325 rsi 236 rsif 236 rsn 65, 1 9 3, 25 4 , 272, 330 rsp 65, 1 9 3, 25 4 , 272, 330 rtf 2 8 1 rtm 1 9 7, 27 8 rto 206, 2 8 6 r y 236 s s_ 8 2 4 5 s_a 2 4 5 s_c 2 4 5 s_e 2 4 5 s_f 2 4 5 s_ x 2 4 5 sa bit access 66, 76, 176 sa 4 e203 sa5e 203
peb 2255 falc-lh v1.3 data sheet 372 2000-07 sa6e 203 sa6sc 1 9 3, 2 49 sa6s y 210 sa7e 203 sa 8 e 203 sais 67, 1 9 7, 276 scf 5 8 , 217, 2 9 5 sci 1 8 6, 265 scl0 213, 2 9 1 scl1 213, 2 9 1 sdlc 115 sec 1 9 3, 25 4 , 272, 330 second timer 9 5, 150 sf 1 4 0 sflg 266 sfm 1 99 sfr z 2 8 3 sfs 2 4 6, 322 shared flags 172 si 236 sics 6 9 ,20 4 ,2 84 sigm 27 4 signaling controller 1 9 , 66, 76, 115, 12 9 signaling software 362 sim 1 9 3, 272 single channel loop 100, 156 sjr 2 8 6 slc 9 6 137, 1 44 slip 1 9 3, 272 software 362 spn 5 4 , 102, 1 99 ,27 8 sraf 272 sres 1 8 3, 261 srfso 223, 301 sro 2 8 1 srs 2 8 1 srsc 221, 300 ssc0 27 9 ssc1 27 9 ssf 223, 301 ssp 276 supply voltage 335 swd 206 s x sc 221, 300 synchronous pulse receive 37 synchronous pulse transmit 4 0 system clock 33 system clock receive 37 system clock transmit 4 0 system interface 6 9 , 116 t t 4 00ms 1 9 3, 253 t 8 ms 1 9 3, 2 49 tcd1 21 4 test access port 52 time-slot assigner 72, 121 tm 27 9 tra 20 8 transmit clock 32 transmit data in 4 0 transmit data output negative 31 transmit data output positive 30 transmit line 30 transmit line interface 7 9 ,13 4 transmit line monitor 31, 8 0, 136 transmit multiframe begin 3 9 transmit multiframe synchronization 4 2 transmit optical interface data 30, 3 9 transmit path 123 transmit signaling data 4 1 transmit signaling marker 4 2 transmitter 7 8 ,133 transmitter configuration 7 9 transparent mode 171 ts 270, 271 ts16ais 23 4 ts16lfa 23 4 ts16los 23 4 ts16ra 23 4 tsa 20 8 tsif 20 8 tsis 20 8 tt0 201 ttrf 22 4 ,303
peb 2255 falc-lh v1.3 data sheet 373 2000-07 v version status register 332 vfr 2 4 7, 323 vis 51, 1 8 6, 265 vn 256, 332 w write enable 26 x x ais 1 9 5, 27 4 x ap 201 x bs0 300 x bs1 221, 300 x c1 9 3 x c0 272 x c1 272 x co0 203, 2 8 3 x co1 203, 2 8 3 x co2 203, 2 8 3 x cos 203, 2 84 x crc 26 8 x crci 20 4 ,2 84 x dos 213, 2 9 1 x dov 2 4 6, 322 x d u 1 9 3, 251, 272, 327 x fb 213, 2 9 1 x fifo 4 7 x fs 1 9 5 x fw 2 4 6, 322 x hf 1 8 3, 261 x ld 210, 2 8 1 x lhp 207, 2 88 x lo 23 4 , 312 x ls 23 4 ,312 x lsc 1 9 3, 251, 272, 327 x lt 207, 2 88 x l u 210, 2 8 1 x mb 1 9 3, 251, 272, 327 x me 1 8 3, 261 x p 207, 2 88 x pr 1 9 3, 251, 272, 327 x prbs 21 8 ,2 9 7 x ra 200, 27 9 x rep 1 8 3, 2 4 6, 261, 322 x res 1 8 3, 261 x s210 x s13 201 x s15 201 x sif 201 x sis 200 x slp 272, 330 x sn 1 9 3, 256, 272, 331 x sp 1 9 3, 256, 272, 331 x sw 76 x tf 1 8 3, 261 x tm 200, 2 8 1 x to 203, 2 84 xy 200
q ualit?t hat fr uns eine umfassende bedeutung. wir wollen allen ihren ansprchen in der bestm?glichen weise gerecht werden. es geht uns also nicht nur um die produktqualit?t ? unsere anstrengungen gelten gleicherma?en der lieferqualit?t und logistik, dem service und support sowie allen sonstigen beratungs- und betreuungsleistungen. dazu geh?rt eine bestimmte geisteshaltung unserer mitarbeiter. total q uality im denken und handeln gegenber k ollegen, lieferanten und ihnen, unserem k unden. u nsere leitlinie ist jede aufgabe mit ?null fehlern? zu l?sen ? in offener sichtweise auch ber den eigenen arbeitsplatz hinaus ? und uns st?ndig zu verbessern. u nternehmensweit orientieren wir uns dabei auch an ?top? (time optimized processes), um ihnen durch gr??ere schnelligkeit den entscheidenden wettbewerbsvorsprung zu verschaffen. geben sie uns die chance, hohe leistung durch umfassende q ualit?t zu beweisen. wir werden sie berzeugen. q uality takes on an allencompassing significance at semiconductor group. for us it means living up to each and every one of your demands in the best possible way. so we are not only concerned with product quality. we direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. part of this is the very special attitude of our staff. total q uality in thought and deed, towards co-workers, suppliers and you, our customer. our guideline is ?doeverythingwithzerodefects?,inan open manner that is demonstrated beyond your immediate workplace, and to constantly improve. throughout the corporation we also think in terms of time optimized processes (top), greater speed on our part to give you that decisive competitive edge. giveusthechancetoprovethebestof performance through the best of quality ? you will be convinced. http://www.infineon.com total q uality management published by infineon technologies ag

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